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STM32L152C6 数据表(PDF) 21 Page - STMicroelectronics |
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STM32L152C6 数据表(HTML) 21 Page - STMicroelectronics |
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21 / 121 page  STM32L151x6/8/B, STM32L152x6/8/B Functional overview Doc ID 17659 Rev 8 21/121 Figure 2. Clock tree 2. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either 24 MHz or 32 MHz. AHB Prescaler /1, 2..512 APB1 Prescaler /1, 2, 4, 8, 16 PCLK1 HCLK to AHB bus, core, memory and DMA peripherals to APB1 Peripheral Clock Enable Enable Peripheral Clock APB2 Prescaler /1, 2, 4, 8, 16 PCLK2 to TIM9, 10, and 11 peripherals to APB2 Peripheral Clock Enable Enable Peripheral Clock 32 MHz max 32 MHz max to Cortex System timer /8 Clock Enable SYSCLK TIMxCLK TIMxCLK FCLK Cortex free running clock to TIM2,3,4,6 and 7 If (APB1 prescaler =1) x1 else x2 If (APB2 prescaler =1) x1 else x2 32 MHz max HSE OSC 1-24 MHz OSC_IN OSC_OUT HSI RC 16 MHz x3,x4,x6,x8 x12,x16,x24 PLLMUL PLLCLK HSI HSI HSE PLLSRC SW CSS x32,x48 /2,/3,/4 48 MHz USBCLK to USB interface PLLDIV to ADC Peripheral clock enable ADCCLK MHz max 32 OSC32_IN OSC32_OUT LSE OSC 32.768 kHz LSI RC 37 kHz to Independent Watchdog (IWDG) MCO PLLCLK HSI HSE LSE LSI /2,4, 8,16 to RTC MCOSEL RTCCLK RTCSEL[1:0] IWDGCLK SYSCLK /1,2,4, 8,16 MSI LSE LSI to LCD to Timer 9, 10, 11 ETR HSE = High-speed external clock signal LSE = Low-speed external clock signal LSI = Low-speed internal clock signal HSI = High-speed internal clock signal Legend : ai17212c MSI = Multispeed internal clock signal PLLVCO/2 MSI RC MSI |
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