ADRF6750ACPZ-R7 datasheet(32/40 Pages) AD

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ADRF6750

Rev. A | Page 32 of

EVALUATION BOARD

GENERAL DESCRIPTION

This board is designed to allow the user to evaluate the

performance of the ADRF6750. It contains the following:

•

I/Q modulator with integrated fractional-N PLL and VCO

•

SPI and I2C interface connectors

•

DC biasing and filter circuitry for the baseband inputs

•

Low-pass loop filter circuitry

•

10 MHz reference clock

•

Circuitry to support differential signaling to the TESTLO

inputs, including dc biasing circuitry

•

Circuitry to monitor the LOMON outputs

•

SMA connectors for power supplies and the RF output

The evaluation board comes with associated software to allow

easy programming of the ADRF6750.

HARDWARE DESCRIPTION

For more information, refer to the circuit diagram in Figure 71.

Power Supplies

An external 5 V supply (DUT +5 V) drives both an on-chip

3.3 V regulator and the quadrature modulator.

The regulator feeds the VREG1 through VREG6 pins on the

chip with 3.3 V. These pins power the PLL circuitry.

The external reference clock generator can be driven by a 3 V

supply or by a 5 V supply. These supplies can be connected via

an SMA connector, VCO +V.

Recommended Decoupling for Supplies

The external 5 V supply is decoupled initially by a 10 μF capacitor

and then further by a parallel combination of 100 nF and 10 pF

capacitors that are placed as close to the DUT as possible for good

local decoupling. The regulator output should be decoupled by a

parallel combination of 10 pF and 220 μF capacitors. The 220 μF

capacitor decouples broadband noise, which leads to better phase

noise and is recommended for best performance. Case Size C

220 μF capacitors are used to minimize area. A parallel combi-

nation of 100 nF and 10 pF capacitors should be placed on each

VREGx pin. Again, these capacitors are placed as close to the pins

as possible. The impedance of all these capacitors should be low

and constant across a broad frequency range. Surface-mount

multilayered ceramic chip (MLCC) Class II capacitors provide

very low ESL and ESR, which assist in decoupling supply noise

effectively. They also provide good temperature stability and good

aging characteristics. Capacitance also changes vs. applied bias

voltage. Larger case sizes have less capacitance change vs. applied

bias voltage and also lower ESR but higher ESL. The 0603 size

capacitors provide a good compromise. X5R and X7R capacitors

are examples of these types of capacitors and are recommended

for decoupling.

SPI and I2C Interface

The SPI interface connector is a 9-way, D-type connector that can

be connected to the printer port of a PC. Figure 70 shows the

PC cable diagram that must be used with the provided software.

There is also an option to use the I2C interface by using the I2C

receptacle connector. This is a standard I2C connector. Pull-up

resistors are required on the signal lines. The CS pin can be used

to set the slave address of the ADRF6750. CS high sets the slave

address to 0x60, and CS low sets the slave address to 0x40.

9-WAY

FEMALE

D-TYPE

25-WAY

MALE

D-TYPE

TO PC

PRINTER PORT

GND

CLK

DATA

Figure 70. SPI PC Cable Diagram

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