ADRF6750ACPZ-R7 datasheet(33/40 Pages) AD

33 / 40 page

ADRF6750

Rev. A | Page 33 of

Baseband Inputs

The pair of I and Q baseband inputs are served by SMA inputs

so that they can be driven directly from an external generator,

which can also provide the dc bias required. An option is

provided to supply this dc bias through Connector J1, as well.

There is also an option to filter the baseband inputs, although

filtering may not be required, depending on the quality of the

baseband source.

Loop Filter

A fourth-order loop filter is provided at the output of the charge

pump and is required to adequately filter noise from the Σ-Δ

modulator used in the N-divider. With the charge pump current

set to a midscale value of 2.5 mA and using the on-chip VCO,

the loop bandwidth is approximately 60 kHz, and the phase

margin is 55°. C0G capacitors are recommended for use in the

loop filter because they have low dielectric absorption, which is

required for fast and accurate settling time. The use of non-C0G

capacitors may result in a long tail being introduced into the

settling time transient.

Reference Input

The reference input can be supplied by a 10 MHz Taitien clock

generator or by an external clock through the use of Connector J7.

The frequency range of the reference input is from 10 MHz to

20 MHz; if the lower frequency clock is used, the on-chip reference

frequency doubler should be used to set the PFD frequency to

20 MHz to optimize phase noise performance.

TESTLO Inputs

These pins are differential test inputs that allow a variety of

debug options. On this board, the capability is provided to drive

these pins with an external 2× LO signal that is then applied to

an Anaren balun to provide a differential input signal.

When driving the TESTLO pins, the PLL can be bypassed, and the

modulator can be driven directly by this external 2× LO signal.

These inputs also require a dc bias; the following two options

are provided:

•

A dc bias point of 3.3 V through a series inductor path.

A resistor in parallel is provided to de-Q any resonance.

•

A dc bias point, which can be varied from 0 V to 3.3 V

through a resistor divider network. Note that these resistors

should be large in value to ensure that the current drawn is

small and that the resistors have little effect on the input

resistance.

If these pins are not used, ground them by inserting 0 Ω resistors

in R47 and R54.

LOMON Outputs

These pins are differential LO monitor outputs that provide a

replica of the internal LO frequency at 1× LO. The single-ended

power in a 50 Ω load can be programmed to −24 dBm, −18 dBm,

−12 dBm, or −6 dBm. These open-collector outputs must be

terminated to 3.3 V. Because both outputs must be terminated

to 50 Ω, options are provided to terminate to 3.3 V using on-

board 50 Ω resistors or by series inductors (or a ferrite bead),

in which case the 50 Ω termination is provided by the measuring

instrument. If not used, these outputs should be tied to REGOUT.

CCOMPx Pins

The CCOMPx pins are internal compensation nodes that must

be decoupled to ground with a 100 nF capacitor.

MUXOUT

MUXOUT is a test output that allows different internal nodes

to be monitored. It is a CMOS output stage that requires no

termination.

Lock Detect (LDET)

Lock detect is a CMOS output that indicates the state of the

PLL. A high level indicates a locked condition, and a low level

indicates a loss of lock condition.

TXDIS

This input disables the RF output. It can be driven from an exter-

nal stimulus or simply connected high or low by Jumper J18.

RF Output (RFOUT)

RFOUT is the RF output of the ADRF6750. RFOUT MOD

should be grounded in the user application.

ADRF6750ACPZ-R7 数据表(PDF) 33 Page - Analog Devices

ADRF6750ACPZ-R7 数据表(HTML) 33 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

数据表下载