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ADRF6750ACPZ-R7 数据表(PDF) 1 Page - Analog Devices

部件名 ADRF6750ACPZ-R7
功能描述  950 MHz to 1575 MHz Quadrature Modulator
PDF  40 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADRF6750ACPZ-R7 数据表(HTML) 1 Page - Analog Devices

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950 MHz to 1575 MHz Quadrature Modulator
with Integrated Fractional-N PLL and VCO
ADRF6750
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
FEATURES
I/Q modulator with integrated fractional-N PLL and VCO
Gain control span: 47 dB in 1 dB steps
Output frequency range: 950 MHz to 1575 MHz
Output 1 dB compression: 8.5 dBm
Output IP3: 23 dBm
Noise floor: −162 dBm/Hz
Baseband modulation bandwidth: 250 MHz (1 dB)
Output frequency resolution: 1 Hz
Functions with external VCO for extended frequency range
SPI and I2C-compatible serial interfaces
Power supply: 5 V/310 mA
GENERAL DESCRIPTION
The ADRF6750 is a highly integrated quadrature modulator,
frequency synthesizer, and programmable attenuator. The
device covers an operating frequency range from 950 MHz
to 1575 MHz for use in satellite, cellular and broadband
communications.
The ADRF6750 modulator includes a high modulus fractional-N
frequency synthesizer with integrated VCO, providing better
than 1 Hz frequency resolution, and a 47 dB digitally controlled
output attenuator with 1 dB steps.
Control of all the on-chip registers is through a user-selected
SPI interface or I2C interface. The device operates from a single
power supply ranging from 4.75 V to 5.25 V.
FUNCTIONAL BLOCK DIAGRAM
QBBP
QBBN
RSET
TESTLO
TESTLO
SDI/SDA
CLK/SCL
SDO
CS
TXDIS
AGND
DGND
×2
DOUBLER
5-BIT
DIVIDER
REFERENCE
CHARGE
PUMP
CURRENT SETTING
REFIN
REFIN
÷2
PHASE
FREQUENCY
DETECTOR
+
OUTPUT
STAGE
VCO
CORE
0°/90°
REGOUT
VCC1
VCC2
VCC3
VCC4
ADRF6750
VREG1
VREG2
VREG3
VREG4
VREG5
VREG6
LOMONP
LOMONN
RFOUT
47dB
GAIN CONTROL
RANGE
N-COUNTER
INTEGER
REGISTER
FRACTIONAL
REGISTER
MODULUS
225
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
RFCP4 RFCP3 RFCP2 RFCP1
CP
LF3
LF2
LDET
IBBP
IBBN
CCOMP1
CCOMP2
CCOMP3
VTUNE
3.3V
REGULATOR
SPI/
I2C
INTERFACE
Figure 1.


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