ADRF6750

Rev. A | Page 8 of

40

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

1

VCC4

2

IBBP

3

IBBN

4

QBBN

5

QBBP

6

AGND

7

RSET

8

LF3

9

CP

10

LF2

11

VCC1

12

REGOUT

13

VREG1

14

VREG2

35 CCOMP3

36 VREG6

37 AGND

38 VTUNE

39 AGND

40 AGND

41 VCC3

42 VCC3

34 CCOMP2

33 CCOMP1

32 DGND

31 VREG5

30 CLK/SCL

29 SDI/SDA

TOP VIEW

(Not to Scale)

ADRF6750

NOTES

1. CONNECT EXPOSED PAD TO GROUND PLANE VIA

A LOW IMPEDANCE PATH.

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

11, 55, 56, 41, 42, 1

VCC1 to VCC4

Positive Power Supplies for I/Q Modulator. Apply a 5 V power supply to VCC1, which should be

decoupled with power supply decoupling capacitors. Connect VCC2, VCC3, and VCC4 to the same

5 V power supply.

12

REGOUT

3.3 V Output Supply. Drives VREG1, VREG2, VREG3, VREG4, VREG5, and VREG6.

13, 14, 15, 16, 31,

36

VREG1 to

VREG6

Positive Power Supplies for PLL Synthesizer, VCO, and Serial Port. Connect these pins to REGOUT

(3.3 V) and decouple them separately.

6, 19, 20, 21, 24, 37,

39, 40, 46, 47, 49,

50, 51, 52, 53, 54

AGND

Analog Ground. Connect to a low impedance ground plane.

32

DGND

Digital Ground. Connect to the same low impedance ground plane as the AGND pins.

2, 3

IBBP, IBBN

Differential In-Phase Baseband Inputs. These high impedance inputs must be dc-biased to approx-

imately 500 mV dc and should be driven from a low impedance source. Nominal characterized ac

signal swing is 450 mV p-p on each pin. This results in a differential drive of 0.9 V p-p with a 500 mV

dc bias, resulting in a single sideband output power of approximately −1.6 dBm. These inputs are

not self-biased and must be externally biased.

4, 5

QBBN, QBBP

Differential Quadrature Baseband Inputs. These high impedance inputs must be dc-biased to

approximately 500 mV dc and should be driven from a low impedance source. Nominal charac-

terized ac signal swing is 450 mV p-p on each pin. This results in a differential drive of 0.9 V p-p with

a 500 mV dc bias, resulting in a single sideband output power of approximately −1.6 dBm. These

inputs are not self-biased and must be externally biased.

33, 34, 35

CCOMP1 to

CCOMP3

Internal Compensation Nodes. These pins must be decoupled to ground with a 100 nF capacitor.

38

VTUNE

Control Input to the VCO. This voltage determines the output frequency and is derived from

filtering the CP output voltage.

7

RSET

Charge Pump Current Set. Connecting a resistor between this pin and ground sets the maximum

SET

CPmax

R

I

5

.

23

=

9

CP

turn, drives the internal VCO.