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COMBOSMARTMETER 数据表(PDF) 28 Page - Texas Instruments |
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COMBOSMARTMETER 数据表(HTML) 28 Page - Texas Instruments |
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28 / 60 page  START Opcode START Pin DIN 4/f CLK DRDY or t DR tSETTLE ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com START The START pin must be set high (for a minimum of 2 tCLKs) or the START command sent to begin conversions. When START is low, or if the START command has not been sent, the device does not issue a DRDY signal (conversions are halted). When using the START opcode to control conversion, hold the START pin low. In multiple device configurations the START pin is used to synchronize devices (see the Multiple Device Configuration subsection of the SPI Interface section for more details). Settling Time The settling time (tSETTLE) is the time it takes for the converter to output fully-settled data when the START signal is pulled high. Once START is pulled high, DRDY is also pulled high. The next DRDY falling edge indicates that data are ready. Figure 33 shows the timing diagram and Table 7 shows the settling time for different data rates. The settling time depends on fCLK and the decimation ratio (controlled by the DR[2:0] bits in the CONFIG1 register). Table 5 shows the settling time as a function of tCLK. Note that when START is held high and there is a step change in the input signal, it takes 3 tDR for the filter to settle to the new value. Settled data are available on the fourth DRDY pulse. Figure 33. Settling Time Table 7. Settling Time for Different Data Rates DR[2:0] SETTLING TIME UNIT 000 152 tCLK 001 296 tCLK 010 584 tCLK 011 1160 tCLK 100 2312 tCLK 101 4616 tCLK 110 9224 tCLK 28 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS131E04 ADS131E06 ADS131E08 |
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