DSPIC30F0010AT-20ESLASHPF datasheet(90/236 Pages) MICROCHIP

90 / 236 page

dsPIC30F6010A/6015

DS70150C-page 88

14.1

Quadrature Encoder Interface

Logic

A typical incremental (a.k.a. optical) encoder has three

outputs: Phase A, Phase B, and an index pulse. These

signals are useful and often required in position and

speed control of ACIM and SR motors.

The two channels, Phase A (QEA) and Phase B (QEB),

have a unique relationship. If Phase A leads Phase B,

then the direction (of the motor) is deemed positive or

forward. If Phase A lags Phase B, then the direction (of

the motor) is deemed negative or reverse.

A third channel, termed index pulse, occurs once per

revolution and is used as a reference to establish an

absolute position. The index pulse coincides with

Phase A and Phase B, both low.

14.2

16-bit Up/Down Position Counter

Mode

The 16-bit up/down counter counts up or down on

every count pulse, which is generated by the difference

of the Phase A and Phase B input signals. The counter

acts as an integrator, whose count value is proportional

to position. The direction of the count is determined by

the

UPDN

signal,

which

generated

the

Quadrature Encoder Interface logic.

14.2.1

POSITION COUNTER ERROR

CHECKING

Position count error checking in the QEI is provided for

and indicated by the CNTERR bit (QEICON<15>). The

error checking only applies when the position counter

is configured for Reset on the Index Pulse modes

(QEIM<2:0> = ‘110’ or ‘100’). In these modes, the

contents of the POSCNT register are compared with

the values (0xFFFF or MAXCNT + 1, depending on

direction). If these values are detected, an error condi-

tion is generated by setting the CNTERR bit and a QEI

count error interrupt is generated. The QEI count error

interrupt can be disabled by setting the CEID bit

(DFLTCON<8>). The position counter continues to

count encoder edges after an error has been detected.

The POSCNT register continues to count up/down until

a natural rollover/underflow. No interrupt is generated

for the natural rollover/underflow event. The CNTERR

bit is a read/write bit and reset in software by the user.

14.2.2

POSITION COUNTER RESET

The Position Counter Reset Enable bit, POSRES

(QEI<2>), controls whether the position counter is reset

when the index pulse is detected. This bit is only

applicable when QEIM<2:0> = 100 or 110.

If the POSRES bit is set to ‘1’, then the position counter

is reset when the index pulse is detected. If the

POSRES bit is set to ‘0’, then the position counter is not

reset when the index pulse is detected. The position

counter will continue counting up or down, and will be

reset on the rollover or underflow condition.

The interrupt is still generated on the detection of the

index pulse and not on the position counter overflow/

underflow.

14.2.3

COUNT DIRECTION STATUS

As mentioned in the previous section, the QEI logic

generates an UPDN signal, based upon the relation-

ship between Phase A and Phase B. In addition to the

output pin, the state of this internal UPDN signal is

supplied to a SFR bit, UPDN (QEICON<11>) as a read-

only bit. To place the state of this signal on an I/O pin,

the SFR bit, PCDOUT (QEICON<6>), must be 1.

14.3

Position Measurement Mode

There are two measurement modes which are

supported and are termed x2 and x4. These modes are

selected by the QEIM<2:0> mode select bits located in

SFR QEICON<10:8>.

When control bits QEIM<2:0> = 100 or 101, the x2

Measurement mode is selected and the QEI logic only

looks at the Phase A input for the position counter

increment rate. Every rising and falling edge of the

Phase A signal causes the position counter to be incre-

mented or decremented. The Phase B signal is still

utilized for the determination of the counter direction,

just as in the x4 mode.

Within the x2 Measurement mode, there are two

variations of how the position counter is reset:

Position counter reset by detection of index

pulse, QEIM<2:0> = 100.

Position counter reset by match with MAXCNT,

QEIM<2:0> = 101.

When control bits QEIM<2:0> = 110 or 111, the x4

Measurement mode is selected and the QEI logic looks

at both edges of the Phase A and Phase B input sig-

nals. Every edge of both signals causes the position

counter to increment or decrement.

Within the x4 Measurement mode, there are two

variations of how the position counter is reset:

Position counter reset by detection of index

pulse, QEIM<2:0> = 110.

Position counter reset by match with MAXCNT,

QEIM<2:0> = 111.

The x4 Measurement mode provides for finer resolu-

tion data (more position counts) for determining motor

position.

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