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MPC8323CVRAFDCA 数据表(PDF) 20 Page - Freescale Semiconductor, Inc

部件名 MPC8323CVRAFDCA
功能描述  PowerQUICC II Pro Integrated Communications Processor
PDF  82 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MPC8323CVRAFDCA 数据表(HTML) 20 Page - Freescale Semiconductor, Inc

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MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
20
Freescale Semiconductor
Ethernet and MII Management
(management data clock). The MII and RMII are defined for 3.3 V. The electrical characteristics for MDIO
and MDC are specified in Section 8.3, “Ethernet Management Interface Electrical Characteristics.”
8.1.1
DC Electrical Characteristics
All MII and RMII drivers and receivers comply with the DC parametric attributes specified in Table 22.
8.2
MII and RMII AC Timing Specifications
The AC timing specifications for MII and RMII are presented in this section.
8.2.1
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.2.1.1
MII Transmit AC Timing Specifications
Table 23 provides the MII transmit AC timing specifications.
Table 22. MII and RMII DC Electrical Characteristics
Parameter
Symbol
Conditions
Min
Max
Unit
Supply voltage 3.3 V
OVDD
—
2.97
3.63
V
Output high voltage
VOH
IOH = –4.0 mA
OVDD = Min
2.40
OVDD + 0.3
V
Output low voltage
VOL
IOL = 4.0 mA
OVDD = Min
GND
0.50
V
Input high voltage
VIH
——
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
—
–0.3
0.90
V
Input current
IIN
0 V
≤ VIN ≤ OVDD
—±5
μA
Table 23. MII Transmit AC Timing Specifications
At recommended operating conditions with OVDD of 3.3 V ± 10%.
Parameter/Condition
Symbol1
Min
Typical
Max
Unit
TX_CLK clock period 10 Mbps
tMTX
—400
—
ns
TX_CLK clock period 100 Mbps
tMTX
—40
—
ns
TX_CLK duty cycle
tMTXH/tMTX
35
—
65
%
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
tMTKHDX
1
5
15
ns
TX_CLK data clock rise time
tMTXR
1.0
—
4.0
ns



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