AD7652

TIMING SPECIFICATIONS

Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted

Parameter

Symbol

Min

Typ

Max

Unit

Refer to Figure 26 and Figure 27

Convert Pulsewidth

10

ns

Time between Conversions

2

µs

CNVST LOW to BUSY HIGH Delay

35

ns

BUSY HIGH All Modes Except Master Serial Read after Convert

1.25

µs

Aperture Delay

2

ns

End of Conversion to BUSY LOW Delay

10

ns

Conversion Time

1.25

µs

Acquisition Time

750

ns

RESET Pulsewidth

10

ns

Refer to Figure 28, Figure 29, and

(Parallel Interface Modes)

CNVST LOW to DATA Valid Delay

1.25

µs

DATA Valid to BUSY LOW Delay

12

ns

Bus Access Request to DATA Valid

45

ns

Bus Relinquish Time

5

15

ns

Refer to Figure 32 and Figure 33 (Master Serial Interface Modes)1

CS LOW to SYNC Valid Delay

10

ns

CS LOW to Internal SCLK Valid Delay1

10

ns

CS LOW to SDOUT Delay

10

ns

CNVST LOW to SYNC Delay

525

ns

SYNC Asserted to SCLK First Edge Delay

3

ns

Internal SCLK Period2

25

40

ns

Internal SCLK HIGH2

12

ns

Internal SCLK LOW2

7

ns

SDOUT Valid Setup Time2

4

ns

SDOUT Valid Hold Time2

2

ns

SCLK Last Edge to SYNC Delay2

3

ns

CS HIGH to SYNC HI-Z

10

ns

CS HIGH to Internal SCLK HI-Z

10

ns

CS HIGH to SDOUT HI-Z

10

ns

BUSY HIGH in Master Serial Read after Convert2

See Table 4

CNVST LOW to SYNC Asserted Delay

1.25

µs

SYNC Deasserted to BUSY LOW Delay

25

ns

Refer to

and

(Slave Serial Interface Modes)1

External SCLK Setup Time

5

ns

External SCLK Active Edge to SDOUT Delay

3

18

ns

SDIN Setup Time

5

ns

SDIN Hold Time

5

ns

External SCLK Period

25

ns

External SCLK HIGH

10

ns

External SCLK LOW

10

ns

Figure 30

Figure 34

Figure 35

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