AD7652AST datasheet(15/28 Pages) AD

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AD7652

CIRCUIT INFORMATION

SWA

COMP

SWB

REF

REFGND

LSB

MSB

32,768C

INGND

16,384C

65,536C

CONTROL

LOGIC

SWITCHES

CONTROL

BUSY

OUTPUT

CODE

02964-0-005

CNVST

Figure 20. ADC Simplified Schematic

igure 20

The AD7652 is a very fast, low power, single supply, precise

16-bit analog-to-digital converter (ADC).

During the acquisition phase, the common terminal of the array

tied to the comparator's positive input is connected to AGND

via SWA. All independent switches are connected to the analog

input IN. Thus, the capacitor array is used as a sampling

capacitor and acquires the analog signal on IN. Similarly, the

dummy capacitor acquires the analog signal on INGND.

The AD7652 provides the user with an on-chip track/hold,

successive approximation ADC that does not exhibit any

pipeline or latency, making it ideal for multiple multiplexed

channel applications.

When CNVST goes LOW, a conversion phase is initiated. When

the conversion phase begins, SWA and SWB are opened. The

capacitor array and dummy capacitor are then disconnected

from the inputs and connected to REFGND. Therefore, the

differential voltage between IN and INGND captured at the end

of the acquisition phase is applied to the comparator inputs,

causing the comparator to become unbalanced. By switching

each element of the capacitor array between REFGND and REF,

the comparator input varies by binary weighted voltage steps

(VREF/2, VREF/4, …VREF/65536). The control logic toggles these

switches, starting with the MSB, to bring the comparator back

into a balanced condition.

The AD7652 can be operated from a single 5 V supply and can

be interfaced to either 5 V or 3 V digital logic. It is housed in

either a 48-lead LQFP or a 48-lead LFCSP that saves space and

allows flexible configurations as either a serial or parallel inter-

face. The AD7652 is pin-to-pin compatible with PulSAR ADCs.

CONVERTER OPERATION

The AD7652 is a successive-approximation ADC based on a

charge redistribution DAC. F

shows a simplified sche-

matic of the ADC. The capacitive DAC consists of an array of 16

binary weighted capacitors and an additional LSB capacitor. The

comparator’s negative input is connected to a dummy capacitor

of the same value as the capacitive DAC array.

After this process is completed, the control logic generates the

ADC output code and brings the BUSY output LOW.

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