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AD7652AST 数据表(PDF) 6 Page - Analog Devices

部件名 AD7652AST
功能描述  16-Bit 500 kSPS PulSARTM Unipolar ADC with Reference
PDF  28 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD7652AST 数据表(HTML) 6 Page - Analog Devices

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AD7652
Table 4. Serial Clock Timings in Master Read after Convert
DIVSCLK[1]
0
0
1
1
DIVSCLK[0]
Symbol
0
1
0
1
Unit
SYNC to SCLK First Edge Delay Minimum
t18
3
17
17
17
ns
Internal SCLK Period Minimum
t19
25
50
100
200
ns
Internal SCLK Period Maximum
t19
40
70
140
280
ns
Internal SCLK HIGH Minimum
t20
12
22
50
100
ns
Internal SCLK LOW Minimum
t21
7
21
49
99
ns
SDOUT Valid Setup Time Minimum
t22
4
18
18
18
ns
SDOUT Valid Hold Time Minimum
t23
2
4
30
80
ns
SCLK Last Edge to SYNC Delay Minimum
t24
3
55
130
290
ns
BUSY HIGH Width Maximum
t24
2
2.5
3.5
5.75
µs
Rev. 0 | Page 6 of 28



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