AD7652

SLAVE SERIAL INTERFACE

External Clock

The AD7652 is configured to accept an externally supplied

serial data clock on the SCLK pin when the EXT/INT pin is held

HIGH. In this mode, several methods can be used to read the

data. The external serial clock is gated by CS. When CS and RD

are both LOW, the data can be read after each conversion or

during the following conversion. The external clock can be

either a continuous or a discontinuous clock. A discontinuous

clock can be either normally HIGH or normally LOW when

inactive. F

and F

show the detailed timing

diagrams of these methods.

igure 34

Figure 34. Slave Serial Data Timing for Reading (Read after Convert)

igure 35

Figure 35. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)

While the AD7652 is performing a bit decision, it is important

that voltage transients be avoided on digital input/output pins or

degradation of the conversion result could occur. This is

particularly important during the second half of the conversion

phase because the AD7652 provides error correction circuitry

that can correct for an improper bit decision made during the

first half of the conversion phase. For this reason, it is

recommended that when an external clock is being provided, it

is a discontinuous clock that is toggling only when BUSY is

LOW, or, more importantly, that it does not transition during the

latter half of BUSY HIGH.

SCLK

SDOUT

D15

D14

D1

D0

D13

X15

X14

X13

X1

X0

Y15

Y14

BUSY

SDIN

INVSCLK = 0

X15

X14

X

1

2

3

14

151617

18

02964-0-017

EXT/INT = 1

RD

RD = 0

SDOUT

SCLK

D1

D0

X

D15

D14

D13

12

3

14

15

16

BUSY

EXT/INT = 1

INVSCLK = 0

02965-0-018

CNVST

CS

RD = 0

Rev. 0 | Page 22 of 28