ADM1275-2ARQZ-R7 datasheet(35/48 Pages) AD

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Data Sheet

ADM1275

Rev. D | Page 35 of 48

SMBus ALERT RESPONSE ADDRESS

The SMBus alert response address (ARA) is a special address

that can be used by the bus host to locate any devices that need

to talk to it. A host typically uses a hardware interrupt pin to

monitor the SMBus ALERT pins of a number of devices. When

the host interrupt occurs, the host issues a message on the bus

using the SMBus receive byte or receive byte with PEC protocol.

The special address used by the host is 0x0C. Any devices that

have an SMBAlert signal return their own 7-bit address as the

seven MSBs of the data byte. The LSB value is not used and can

be either 1 or 0. The host reads the device address from the

received data byte and proceeds to handle the alert condition.

More than one device may have an active SMBAlert signal and

attempt to communicate with the host. In this case, the device

with the lowest address dominates the bus and succeeds in

transmitting its address to the host. The device that succeeds

disables its SMBus alert signal. If the host sees that the SMBus

alert signal is still low, it continues to read addresses until all

devices that need to talk to it have successfully transmitted their

addresses.

EXAMPLE USE OF SMBus ALERT RESPONSE

ADDRESS

The full sequence of steps that occurs when an SMBAlert is

generated and cleared is as follows:

1. A fault or warning is enabled using the ALERT1_CONFIG

command, and the corresponding status bit for the fault or

warning goes from 0 to 1, indicating that the fault/warning

has just become active.

2. The GPOx/ALERTx pin becomes active (low) to signal that

an SMBAlert is active.

3. The host processor issues an SMBus alert response address

to determine which device has an active alert.

4. If there are no other active alerts from devices with lower

I2C addresses, this device makes the GPOx/ALERTx pin

inactive (high) during the NACK bit period after it sends

its address to the host processor.

5. If the GPOx/ALERTx pin stays low, the host processor must

continue to issue SMBus alert response address commands

to devices to find out the addresses of all devices whose

status it must check.

6. The ADM1275 continues to operate with the GPOx/ALERTx

pin inactive and the contents of the status bytes unchanged

until the host reads the status bytes and clears them, or until

a new fault occurs. That is, if a status bit for a fault/warning

that is enabled on the GPOx/ALERTx pin and that was not

already active (equal to 1) goes from 0 to 1, a new alert is

generated, causing the GPOx/ALERTx pin to become

active again.

ADM1275-2ARQZ-R7 数据表(PDF) 35 Page - Analog Devices

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