PE9701 datasheet(9/13 Pages) PSEMI

9 / 13 page

Product Specification

PE9701

Page 9 of 13

Document No. 70-0035-02

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Serial Interface Mode

Serial Interface Mode is selected by setting the

Bmode input “low” and the Smode input “high”.

While the E_WR input is “low” and the S_WR

input is “low”, serial input data (Sdata input), B0 to

B19, is clocked serially into the primary register on

the rising edge of Sclk, MSB (B0) first.

The

contents from the primary register are transferred

into the secondary register on the rising edge of

either S_WR or Hop_WR according to the timing

diagram shown in Figure 6. Data is transferred to

the counters as shown in Table 7 on page 9.

The double buffering provided by the primary and

secondary registers allows for “ping-pong” counter

control using the FSELS input. When FSELS is

“high”, the primary register contents set the

counter inputs.

When FSELS is “low”, the

secondary register contents are utilized.

While the E_WR input is “high” and the S_WR

input is “low”, serial input data (Sdata input), B0 to

B7, is clocked serially into the enhancement

The enhancement register is double buffered to

prevent inadvertent control changes during serial

loading, with buffer capture of the serially-entered

data performed on the falling edge of E_WR

according to the timing diagram shown in Figure

6. After the falling edge of E_WR, the data

provides control bits as shown in Table 8 with bit

functionality enabled by asserting the

Enh input

“low”.

Direct Interface Mode

Direct Interface Mode is selected by setting the

Bmode input “high”.

Counter control bits are set directly at the pins as

shown in Table 7. In Direct Interface Mode, main

counter inputs M7 and M8, and R Counter inputs

R4 and R5 are internally forced low (“0”).

MSB (first in)

(last in) LSB

Table 7. Primary Register Programming

Table 8. Enhancement Register Programming

*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.

*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.

MSB (first in)

(last in) LSB

Interface

Mode

Enh

Bmode

Smode

Pre_en

Parallel

M2_WR rising edge load

M1_WR rising edge load

A_WR rising edge load

Serial*

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

Direct

Pre_en

Interface

Mode

Enh

Bmode

Smode

Reserved

Power

down

Counter

load

MSEL

output

Prescaler

output

fc, fp OE

Parallel

E_WR rising edge load

Serial*

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