Product Specification

PE9701

Page 4 of 13

©2003-2006 Peregrine Semiconductor Corp. All rights reserved.

Document No. 70-0035-02

│ UltraCMOS™ RFIC Solutions

Table 1. Pin Descriptions (continued)

Note 1:

Note 2:

All digital input pins have 70 k

Ω pull-down resistors to ground.

Pin No.

Pin Name

Interface Mode

Type

Description

31

ALL

(Note 1)

32

Dout

Serial, Parallel

Output

Data Out. The MSEL signal and the raw prescaler output are available on Dout

through enhancement register programming.

33

ALL

(Note 1)

Same as pin 1.

34

Cext

ALL

Output

Logical “OR” of PD_U and PD_D terminated through an on chip, 2 k

Ω series resistor.

Connecting Cext to an external capacitor will low pass filter the input to the inverting

amplifier used for driving LD.

35

ALL

(Note 1)

Same as pin 1.

36

CP

ALL

Output

37

NC

ALL

No connection.

38

ALL

(Note 1)

39

ALL

Output

Monitor pin for reference divider output. Switching activity can be disabled through

40

GND

ALL

Ground.

41

GND

ALL

Ground.

42

ALL

Input

Reference frequency input.

43

LD

ALL

Output,

OD

Lock detect and open drain logical inversion of Cext. When the loop is in lock, LD is

high impedance, otherwise LD is a logic low (“0”).

44

Enh

Serial, Parallel

Input

Enhancement mode. When asserted low (“0”), enhancement register bits are

functional.