Product Specification

PE9701

Page 2 of 13

©2003-2006 Peregrine Semiconductor Corp. All rights reserved.

Document No. 70-0035-02

│ UltraCMOS™ RFIC Solutions

Table 1. Pin Descriptions

Figure 2. Pin Configurations (Top View)

44-lead CQFJ

Figure 3. Package Type

11

12

13

14

15

16

17

10

9

8

7

6

54321 44 43 42 41 40

35

34

33

32

31

30

29

36

37

38

39

18 19 20 21 22 23 24 25 26 27 28

D

D

D

D

V

DD

V

DD

S_WR, D

Sdata, D

Sclk, D

FSELS, D

GND

GND

f

p

V

D

out

V

DD

C

ext

V

DD

CP

N/C

V

f

c

Pin No.

Pin Name

Interface Mode

Type

Description

1

ALL

(Note 1)

Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing

recommended.

2

Direct

Input

R Counter bit0 (LSB).

3

Direct

Input

R Counter bit1.

4

Direct

Input

R Counter bit2.

5

Direct

Input

R Counter bit3.

6

GND

ALL

(Note 1)

Ground.

7

Parallel

Input

Parallel data bus bit0 (LSB).

Direct

Input

M Counter bit0 (LSB).

8

Parallel

Input

Parallel data bus bit1.

Direct

Input

M Counter bit1.

9

Parallel

Input

Parallel data bus bit2.

Direct

Input

M Counter bit2.

10

Parallel

Input

Parallel data bus bit3.

Direct

Input

M Counter bit3.

11

ALL

(Note 1)

Same as pin 1.

12

ALL

(Note 1)

Same as pin 1.

13

S_WR

Serial

Input

Serial load enable input. While S_WR is “low”, Sdata can be serially clocked.

Primary register data is transferred to the secondary register on S_WR or Hop_WR

rising edge.

Parallel

Input

Parallel data bus bit4

Direct

Input

M Counter bit4