ADE7978 datasheet(30/120 Pages) AD

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ADE7978/ADE7933/ADE7932

Data Sheet

Rev. 0 | Page 30 of 120

THEORY OF OPERATION

ADE7933/ADE7932 ANALOG INPUTS

The ADE7933 has three analog input channels: one current

channel and two voltage channels. The ADE7932 does not

include the second voltage channel. The current channel has

two fully differential voltage input pins, IP and IM, that accept

a maximum differential signal of ±31.25 mV.

The maximum differential signal level on the IP and IM pins

with respect to GNDISO is also ±31.25 mV. However, the maxi-

mum signal allowed at the IM input is ±25 mV. Figure 37 shows

a schematic of the current channel input and its relation to the

maximum IM pin voltage.

VIM

VIP

+31.25mV

VIP

VIP = ±31.25mV MAX PEAK

VIM = ±25mV MAX

–31.25mV

Figure 37. Maximum Input Level, Current Channel

The current channel is used to sense the voltage across a shunt.

In this case, one pole of the shunt becomes the ground of the

meter (see Figure 101) and, therefore, the current channel is

used in a pseudo differential configuration, similar to the

voltage channel configuration (see Figure 38).

The voltage channels have two pseudo differential, single-ended

voltage input pins: V1P and V2P. These single-ended voltage

inputs have a maximum input voltage of ±500 mV with respect

to VM. The maximum signal allowed at the VM input is ±25 mV.

Figure 38 shows a schematic of the voltage channel inputs and

their relation to the maximum VM pin voltage.

V1P OR

V2P

+500mV

V1 = ±500mV MAX PEAK

VM = ±25mV MAX

–500mV

Figure 38. Maximum Input Level, Voltage Channels

ANALOG-TO-DIGITAL CONVERSION

The ADE7933/ADE7932 have three second-order Σ-Δ ADCs.

For simplicity, the block diagram in Figure 39 shows a first-order

Σ-Δ ADC. The converter is composed of the Σ-Δ modulator and

the digital low-pass filter, separated by the digital isolation block.

A Σ-Δ modulator converts the input signal into a continuous

serial stream of 1s and 0s at a rate determined by the sampling

clock. In the ADE7933/ADE7932, the sampling clock is equal to

1.024 MHz (CLKIN/16). The 1-bit DAC in the feedback loop is

driven by the serial data stream. The DAC output is subtracted

from the input signal. If the loop gain is high enough, the average

value of the DAC output (and, therefore, the bit stream) can

approach that of the input signal level.

For any given input value in a single sampling interval, the data

from the 1-bit ADC is virtually meaningless. A meaningful result

is obtained only when a large number of samples is averaged. This

averaging is carried out in the second part of the ADC, the digital

low-pass filter, after the data is passed through the digital isolators.

By averaging a large number of bits from the modulator, the low-

pass filter can produce 24-bit data-words that are proportional

to the input signal level.

DIGITAL

LOW-PASS

FILTER

ADE7978

–

CLKIN/16

INTEGRATOR

VREF

1-BIT DAC

LATCHED

COMPARATOR

ANALOG

LOW-PASS

FILTER

.....10100101.....

–

DIGITAL

ISOLATION

BARRIER

ADE7932/ADE7933

Figure 39. First-Order Σ-∆ ADC

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