STM32F373VC datasheet(25/131 Pages) STMICROELECTRONICS

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STM32F37xxx

Functional overview

ALERT protocol management. They also have a clock domain independent from the CPU

clock, allowing the application to wake up the MCU from Stop mode on address match.

The I2C interfaces can be served by the DMA controller

Refer to Table 7 for the differences between I2C1 and I2C2.

3.20

Universal synchronous/asynchronous receiver transmitter

(USART)

The STM32F373x embeds three universal synchronous/asynchronous receiver transmitters

(USART1, USART2 and USART3).

All USARTs interfaces are able to communicate at speeds of up to 9 Mbit/s.

They provide hardware management of the CTS and RTS signals, they support IrDA SIR

ENDEC, the multiprocessor communication mode, the single-wire half-duplex

communication mode, Smartcard mode (ISO/IEC 7816 compliant), autobaudrate feature

and have LIN Master/Slave capability. The USART interfaces can be served by the DMA

controller.

Refer to Table 8 for the features of USART1, USART2 and USART3.

Table 7. STM32F373x I2C implementation

I2C features(1)

1. X = supported.

I2C1

I2C2

7-bit addressing mode

10-bit addressing mode

Standard mode (up to 100 kbit/s)

Fast mode (up to 400 kbit/s)

Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)

Independent clock

SMBus

Wakeup from STOP

Table 8. STM32F373x USART implementation

USART modes/features(1)

USART1

USART2

USART3

Hardware flow control for modem

Continuous communication using DMA

Multiprocessor communication

Synchronous mode

Smartcard mode

Single-wire half-duplex communication

IrDA SIR ENDEC block

LIN mode

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