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AGLP030 数据表(PDF) 57 Page - Microsemi Corporation |
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AGLP030 数据表(HTML) 57 Page - Microsemi Corporation |
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57 / 134 page ![]() IGLOO PLUS Low Power Flash FPGAs Revision 16 2-43 Fully Registered I/O Buffers with Asynchronous Clear Figure 2-13 • Timing Model of the Registered I/O Buffers with Asynchronous Clear CLK CLR Data_out Data Y AA EOUT DOUT Core Array DQ DFN1C1 CLR DQ DFN1C1 CLR DQ DFN1C1 CLR CC DD EE FF LL HH JJ INBUF CLKBUF Data Input I/O Register with Active High Clear Positive-Edge Triggered Data Output Register and Enable Output Register with Active High Clear Positive-Edge Triggered |
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