AGLP030 datasheet(91/134 Pages) MICROSEMI

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IGLOO PLUS Low Power Flash FPGAs

Revision 16

2-77

1.2 V DC Core Voltage

Table 2-97 • FIFO

Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V

Parameter

Description

Std.

Units

tENS

REN, WEN Setup Time

3.44

tENH

REN, WEN Hold Time

0.26

tBKS

BLK Setup Time

0.30

tBKH

BLK Hold Time

0.00

tDS

Input Data (WD) Setup Time

1.30

tDH

Input Data (WD) Hold Time

0.41

tCKQ1

Clock High to New Data Valid on RD (flow-through)

5.67

tCKQ2

Clock High to New Data Valid on RD (pipelined)

3.02

tRCKEF

RCLK High to Empty Flag Valid

6.02

tWCKFF

WCLK High to Full Flag Valid

5.71

tCKAF

Clock High to Almost Empty/Full Flag Valid

22.17

tRSTFG

RESET Low to Empty/Full Flag Valid

5.93

tRSTAF

RESET Low to Almost Empty/Full Flag Valid

21.94

tRSTBQ

RESET Low to Data Out Low on RD (flow-through)

3.41

RESET Low to Data Out Low on RD (pipelined)

3.41

tREMRSTB

RESET Removal

1.02

tRECRSTB

RESET Recovery

5.48

tMPWRSTB

RESET Minimum Pulse Width

1.18

tCYC

Clock Cycle Time

10.90

FMAX

Maximum Frequency for FIFO

MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

AGLP030 数据表(PDF) 91 Page - Microsemi Corporation

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