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AGLP030 数据表(PDF) 61 Page - Microsemi Corporation |
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AGLP030 数据表(HTML) 61 Page - Microsemi Corporation |
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61 / 134 page  IGLOO PLUS Low Power Flash FPGAs Revision 16 2-47 Output Register Timing Characteristics 1.5 V DC Core Voltage Figure 2-15 • Output Register Timing Diagram Clear DOUT CLK Data_out Preset 50% tOSUD tOHD 50% 50% tOCLKQ 1 0 tORECPRE tOREMPRE tORECCLR tOREMCLR tOWCLR tOWPRE tOPRE2Q tOCLR2Q tOCKMPWH tOCKMPWL 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% Table 2-76 • Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tOCLKQ Clock-to-Q of the Output Data Register 0.66 ns tOSUD Data Setup Time for the Output Data Register 0.33 ns tOHD Data Hold Time for the Output Data Register 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 0.82 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 0.88 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.24 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.24 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.19 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.19 ns tOCKMPWH Clock Minimum Pulse Width High for the Output Data Register 0.31 ns tOCKMPWL Clock Minimum Pulse Width Low for the Output Data Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. |
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