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AGLP030 数据表(PDF) 1 Page - Microsemi Corporation |
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AGLP030 数据表(HTML) 1 Page - Microsemi Corporation |
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1 / 134 page  December 2012 I © 2012 Microsemi Corporation IGLOO PLUS Low Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power • 1.2 V to 1.5 V Core Voltage Support for Low Power • Supports Single-Voltage System Operation • 5 µW Power Consumption in Flash*Freeze Mode • Low Power Active FPGA Operation • Flash*Freeze Technology Enables Ultra-Low Power Consumption while Maintaining FPGA Content • Configurable Hold Previous State, Tristate, HIGH, or LOW State per I/O in Flash*Freeze Mode • Easy Entry To / Exit From Ultra-Low Power Flash*Freeze Mode Feature Rich • 30 k to 125 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 212 User I/Os Reprogrammable Flash Technology • 130-nm, 7-Layer Metal, Flash-Based CMOS Process • Instant On Level 0 Support • Single-Chip Solution • Retains Programmed Design When Powered Off • 250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System Performance In-System Programming (ISP) and Security • ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532–compliant)† • FlashLock® Designed to Secure FPGA Contents High-Performance Routing Hierarchy • Segmented, Hierarchical Routing and Clock Structure Advanced I/O • 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—4 Banks per Chip on All IGLOO® PLUS Devices • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3V /2.5 V / 1.8V /1.5 V/1.2 V • Selectable Schmitt Trigger Inputs • Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V • Wide Range Power Supply Voltage Support per JESD8-12, Allowing I/Os to Operate from 1.14 V to 1.575 V • I/O Registers on Input, Output, and Enable Paths • Hot-Swappable and Cold-Sparing I/Os • Programmable Output Slew Rate and Drive Strength • Weak Pull-Up/-Down • IEEE 1149.1 (JTAG) Boundary Scan Test • Pin-Compatible Small-Footprint Packages across the IGLOO PLUS Family Clock Conditioning Circuit (CCC) and PLL† • Six CCC Blocks, One with an Integrated PLL • Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback • Wide Input Frequency Range (1.5 MHz up to 250 MHz) Embedded Memory • 1 kbit of FlashROM User Nonvolatile Memory • SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)† • True Dual-Port SRAM (except ×18)† † The AGLP030 device does not support this feature. Table 1 • IGLOO PLUS Product Family IGLOO PLUS Devices AGLP030 AGLP060 AGLP125 System Gates 30,000 60,000 125,000 Typical Equivalent Macrocells 256 512 1,024 VersaTiles (D-flip-flops) 792 1,584 3,120 Flash*Freeze Mode (typical, µW) 5 10 16 RAM Kbits (1,024 bits) – 18 36 4,608-Bit Blocks – 4 8 Secure (AES) ISP – Yes Yes FlashROM Kbits 1 1 1 Integrated PLL in CCCs 1 – 1 1 VersaNet Globals 2 618 18 I/O Banks 4 4 4 Maximum User I/Os 120 157 212 Package Pins CS VQ CS201, CS289 VQ128 CS201, CS289 VQ176 CS281, CS289 Notes: 1. AGLP060 in CS201 does not support the PLL. 2. Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125. Revision 16 |
类似零件编号 - AGLP030 |
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类似说明 - AGLP030 |
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