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AGLP030 数据表(PDF) 84 Page - Microsemi Corporation

部件名 AGLP030
功能描述  IGLOO PLUS Low Power Flash FPGAs
PDF  134 Pages
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制造商  MICROSEMI [Microsemi Corporation]
网页  http://www.microsemi.com
标志 MICROSEMI - Microsemi Corporation

AGLP030 数据表(HTML) 84 Page - Microsemi Corporation

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IGLOO PLUS DC and Switching Characteristics
2-70
Revision 16
1.2 V DC Core Voltage
Table 2-94 • RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
Description
Std.
Units
tAS
Address setup time
1.28
ns
tAH
Address hold time
0.25
ns
tENS
REN, WEN setup time
1.25
ns
tENH
REN, WEN hold time
0.25
ns
tBKS
BLK setup time
2.54
ns
tBKH
BLK hold time
0.25
ns
tDS
Input data (DIN) setup time
1.10
ns
tDH
Input data (DIN) hold time
0.55
ns
tCKQ1
Clock High to new data valid on DOUT (output retained, WMODE = 0)
5.51
ns
Clock High to new data valid on DOUT (flow-through, WMODE = 1)
4.77
ns
tCKQ2
Clock High to new data valid on DOUT (pipelined)
2.82
ns
tC2CWWL1
Address collision clk-to-clk delay for reliable write after write on same address –
applicable to closing edge
0.30
ns
tC2CRWH1
Address collision clk-to-clk delay for reliable read access after write on same address –
applicable to opening edge
0.32
ns
tC2CWRH1
Address collision clk-to-clk delay for reliable write access after read on same address –
applicable to opening edge
0.44
ns
tRSTBQ
RESET Low to data out Low on DOUT (flow-through)
3.21
ns
RESET Low to data out Low on DOUT (pipelined)
3.21
ns
tREMRSTB
RESET removal
0.93
ns
tRECRSTB
RESET recovery
4.94
ns
tMPWRSTB RESET minimum pulse width
1.18
ns
tCYC
Clock cycle time
10.90
ns
FMAX
Maximum frequency
92
MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.



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