AM29F100 datasheet(17/36 Pages) AMD

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Am29F100

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that

indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output, sev-

eral RY/BY# pins can be tied together in parallel with a

pull-up resistor to VCC.

If the output is low (Busy), the device is actively erasing

or programming. (This includes programming in the

Erase Suspend mode.) If the output is high (Ready),

the device is ready to read array data (including during

the Erase Suspend mode), or is in the standby mode.

Table 6 shows the outputs for RY/BY#. The timing dia-

grams for read, reset, program, and erase shows the

relationship of RY/BY# to other signals.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is

valid after the rising edge of the final WE# pulse in the

command sequence (prior to the program or erase op-

eration), and during the sector erase time-out.

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. (The system may use either OE# or

CE# to control the read cycles.) When the operation is

complete, DQ6 stops toggling.

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 tog-

gles for approximately 100

µs, then returns to reading

array data. If not all selected sectors are protected,

the Embedded Erase algorithm erases the unpro-

tected sectors, and ignores the selected sectors that

are protected.

If a program address falls within a protected sector,

DQ6 toggles for approximately 2

µs after the program

command sequence is written, then returns to reading

array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

The Write Operation Status table shows the outputs for

Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit

algorithm, and to the Toggle Bit Timings figure in the

“AC Characteristics” section for the timing diagram.

Reading Toggle Bit DQ6

Refer to Figure 5 for the following discussion. When-

ever the system initially begins reading toggle bit sta-

tus, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, a

system would note and store the value of the toggle

bit after the first read. After the second read, the sys-

tem would compare the new value of the toggle bit

with the first. If the toggle bit is not toggling, the device

has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the fol-

lowing read cycle.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the

system also should note whether the value of DQ5 is

high (see the section on DQ5). If it is, the system

should then determine again whether the toggle bit is

toggling, since the toggle bit may have stopped tog-

gling just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the

device did not complete the operation successfully, and

the system must write the reset command to return to

reading array data.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has not

gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles, de-

termining the status as described in the previous para-

graph. Alternatively, it may choose to perform other

system tasks. In this case, the system must start at the

beginning of the algorithm when it returns to determine

the status of the operation (top of Figure 5).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure

condition that indicates the program or erase cycle was

not successfully completed.

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously

programmed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the operation has

exceeded the timing limits, DQ5 produces a “1.”

Under both these conditions, the system must issue

the reset command to return the device to reading

array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If addi-

tional sectors are selected for erasure, the entire time-

out also applies after each additional sector erase

command. When the time-out is complete, DQ3

switches from “0” to “1.” The system may ignore DQ3

if the system can guarantee that the time between ad-

ditional sector erase commands will always be less

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