AM29F400AT datasheet(16/35 Pages) AMD

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Am29F400AT/Am29F400AB

PRELIMINARY

RY/BY

Ready/Busy

The Am29F400A provides a RY/BY open-drain output

pin as a way to indicate to the host system that the Em-

bedded Algorithms are either in progress or have been

completed. If the output is low, the device is busy with

either a program or erase operation. If the output is

high, the device is ready to accept any read/write or

erase operation. When the RY/BY pin is low, the device

will not accept any additional program or erase com-

mands with the exception of the Erase Suspend com-

mand. If the Am29F400A is placed in an Erase

Suspend mode, the RY/BY output will be high.

During programming, the RY/BY pin is driven low after

the rising edge of the fourth WE pulse. During an erase

operation, the RY/BY pin is driven low after the rising

edge of the sixth WE pulse. The RY/BY pin should be

ignored while RESET is at VIL. Refer to Figure 12 for a

detailed timing diagram.

Since this is an open-drain output, several RY/BYpins

can be tied together in parallel with a pull-up resistor

to VCC.

RESET

Hardware Reset

The Am29F400A device may be reset by driving the

RESET pin to VIL. The RESET pin must be kept low

(VIL) for at least 500 ns. Any operation in progress will

be terminated and the internal state machine will be

reset to the read mode 20

µs after the RESET pin is

driven low. Furthermore, once the RESET pin goes

high, the device requires an additional 50 ns before it

will allow read access. When the RESET pin is low, the

device will be in the standby mode for the duration of

the pulse and all the data output pins will be tri-stated.

If a hardware reset occurs during a program or erase

operation, the data at that particular location will

be indeterminate.

The RESET pin may be tied to the system reset input.

Therefore, if a system reset occurs during the Embed-

ded Program or Erase Algorithm, the device will be au-

tomatically reset to read mode and this will enable the

system’s microprocessor to read the boot-up ﬁrmware

from the Flash memory.

Byte/Word Conﬁguration

The BYTE pin selects the byte (8-bit) mode or word

(16 bit) mode for the Am29F400A device. When this

pin is driven high, the device operates in the word (16

bit) mode. The data is read and programmed

at DQ0–DQ15. When this pin is driven low, the de-

vice operates in byte (8 bit) mode. Under this mode,

the DQ15/A-1 pin becomes the lowest address bit

and DQ8–DQ14 bits are tri-stated. However, the

command bus cycle is always an 8-bit operation and

hence commands are written at DQ0–DQ7 and the

DQ8–DQ15 bits are ignored. Refer to Figures 14 and

15 for the timing diagram.

Data Protection

The Am29F400A is designed to offer protection against

accidental erasure or programming caused by spurious

system level signals that may exist during power transi-

tions. During power up the device automatically resets

the internal state machine in the Read mode. Also, with

its control register architecture, alteration of the mem-

ory contents only occurs after successful completion of

speciﬁc multi-bus cycle command sequences.

The device also incorporates several features to pre-

vent inadver tent write cycles resulting from VCC

power-up and power-down transitions or system noise.

Low VCC Write Inhibit

To avoid initiation of a write cycle during VCC power-up

and power-down, the Am29F400A locks out write cy-

cles for VCC < VLKO (see DC Characteristics section for

voltages). When VCC < VLKO, the command register is

disabled, all inter nal prog r am/er ase circuits

are disabled, and the device resets to the read mode.

The Am29F400A ignores all writes until VCC > VLKO.

The user must ensure that the control pins are in the

correct logic state when VCC > VLKO to prevent unin-

tentional writes.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE, CE, or

WE will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE = VIL,CE

= VIH, or WE = VIH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

Power-Up Write Inhibit

Power-up of the device with WE = CE = VIL and OE =

VIH will not accept commands on the rising edge of WE.

The internal state machine is automatically reset to the

read mode on power-up.

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