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AM7968-125JC 数据表(PDF) 83 Page - Advanced Micro Devices

部件名 AM7968-125JC
功能描述  TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface)
PDF  127 Pages
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制造商  AMD [Advanced Micro Devices]
网页  http://www.amd.com
标志 AMD - Advanced Micro Devices

AM7968-125JC 数据表(HTML) 83 Page - Advanced Micro Devices

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AMD
79
TAXIchip Integrated Circuits Technical Manual
Figure 7-4
Receiver Timing—8-Bit Cascade Mode
Internal
Clock*
SERIN
Serial Data
NRZ Data*
CLK OUT
IGM TAXI #1 =
CNB TAXI #2
DATA OUT
Command
OUT
DSTRB OUT
Command
OUT
DATA OUT
DATA N
DATA N
SYNC
DATA 1
DATA 2
SYNC
SYNC
SYNC
3
2
NO CHANGE
COMMAND 0
11000100011100010001
NO CHANGE
NO CHANGE
NO CHANGE
NO CHANGE
CNB TAXI #1 = 1
NO CHANGE
NO CHANGE
NO CHANGE
NO CHANGE
DATA N–1
NO CHANGE
NO CHANGE
NO CHANGE
NO CHANGE
DATA N
NO CHANGE
1
456
1100010001
DATA 1
DATA 2
11000100011100010001
CSTRB OUT
NO CHANGE
NO CHANGE
NO CHANGE
NO CHANGE
NO CHANGE
CSTRB OUT
DSTRB OUT
* Internal Signals
1100010001
SYNC
SYNC
NO CHANGE
NO CHANGE
TAXI
#2
TAXI
#1
12330E-26
If CNB is HIGH, the Receiver will catch the next valid byte of data and hold it. It will not
attempt to catch any more data until it sees a Sync command from the Transmitter or
until its CNB goes LOW and then HIGH again.
If CNB is held LOW, the Receiver will not attempt to capture any data.
When the Primary Receiver RX1 catches a valid data byte it will raise its IGM (I Got
Mine) so the next Receiver RX2 can catch the next byte and so on down the line. After
all the receivers in the system have received their bytes a Sync must be sent or the next
byte of data will be lost(3) .
Referring to Figure 7-5 for a system of Cascaded Receivers.
(3)
In the Auto-Repeat Configuration, a Sync is not required.



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