AM7968-125JC datasheet(95/127 Pages) AMD

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TAXIchip Integrated Circuit Technical Manual

APPENDIX B

Error Detection Efficiency

When a received data pattern does not represent a valid coding symbol, the TAXI

Receiver asserts the

VLTN pin to indicate that the current data contains an error.

The Receiver cannot detect the occurrence of a bit error that transforms one valid

symbol into another valid but incorrect symbol. This means that the transition error can

change a valid data symbol into a different valid data symbol, or in certain cases a valid

Command symbol and not be flagged by the Violation pin.

A single noise event on the serial link can cause at a minimum a double bit error. Single

bit errors are assumed to be impossible (or at least rare) because NRZI encoding would

require that the voltage level on the link be inverted after the event. There is no known

error mechanism external to the TAXIchip set which could cause this condition. Having

confirmed that all errors are at least 2 bits wide, let us examine the location at which

these errors can exist.

Consider the 4B/5B encoded data pattern for the TAXIchip set in the 8-bit mode. The

output corresponds to two five bit nibbles for each eight bit data byte. Shown below are

four nibbles, or two bytes of encoded data output, with six possible locations for double

bit errors within nibble 1 of Byte 2.

Figure B-1

b7 b6

b2 b1

b7 b6

b2 b1

Byte 2

Byte 1

Nibble 2

Nibble 1

Nibble 2

Nibble 1

MSB

LSB MSB

LSB

Notes:

Error location A corresponds to a double bit error occurring in the Least Significant Bit of nibble 2 and the

Most Significant Bit of nibble 1.

Error locations B, C, D and E occur within the nibble between adjacent bits, and,

Error location F occurs between the LSB of nibble 1 (Byte 2) and the MSB of nibble 2 (Byte 1).

12330E-37

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