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AM7968-125JC 数据表(PDF) 89 Page - Advanced Micro Devices |
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AM7968-125JC 数据表(HTML) 89 Page - Advanced Micro Devices |
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89 / 127 page  AMD 85 TAXIchip Integrated Circuits Technical Manual output data at the same time This also guarantees that the CNB on the first Receiver goes active (HIGH) within 2 gate delays + 20 ns after it goes LOW. This leaves enough time for the first Receiver to capture the (R+1)th byte of data. Figure 7-10 TAXI Receiver—Cascaded In Auto-Repeat Configuration. Configuration 2 12330E-32 CNB IGM CNB IGM CNB IGM CNB IGM SERIN + SERIN - Figure 7-11 TAXI Receiver—Cascaded in Auto-Repeat Configuration. Configuration 3 SERIN+ SERIN– CNB IGM DSTRB CSTRB CNB IGM DSTRB CSTRB CNB IGM DSTRB CSTRB CNB IGM DSTRB CSTRB 12330E-33 In practice, all the AND gates are not required. Using the above equation for X we can calculate a value of R1 for which X is less than 1 byte period at the appropriate fre- quency of operation. Then if the number of receivers to be cascaded is greater than R1, an AND gate is needed for every (R1+1)th Receiver in cascade. The other receivers can be directly connected as shown in Figure 7-11. Syncs in Auto-Repeat Configuration and Recovering from Errors A Sync in Auto-Repeat Configuration acts much like a Sync in Normal Cascade mode. It resets all the Receivers and their IGMs so the upstream (Primary) Receiver receives the next non Sync byte of data. This remains as the method of recovering from byte framing errors. 7.4 Unbalanced Configuration (Am7968/Am7969-125 Only) In reality there is no difference in connection between balanced and Unbalanced Configurations. The name only indicates that the number of Transmit bytes and the number of Receive bytes are unequal. The TAXI Receivers do not care how many data bytes the Transmitter is sending to them. One data byte can be transmitted to several Receivers. The only limitation here is |
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