AM79C973VCW datasheet(2/304 Pages) AMD

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Am79C973/Am79C975

P R E L I M INARY

s Look-Ahead Packet Processing (LAPP) data

handling technique reduces system overhead

by allowing protocol analysis to begin before

the end of a receive frame

s Includes Programmable Inter Packet Gap (IPG)

to address less network aggressive MAC

controllers

s Offers the Modified Back-Off algorithm to

address the Ethernet Capture Effect

s IEEE 1149.1-compliant JTAG Boundary Scan

test access port interface and NAND tree test

mode for board-level production connectivity

test

s Compatible with the existing PCnet Family

driver/diagnostic software

s Software compatible with AMD PCnet Family

and LANCE™/C-LANCE™ register and

descriptor architecture

s Available in 160-pin PQFP and 176-pin TQFP

packages

s Advanced +3.3 V CMOS process technology for

low power operation

GENERAL DESCRIPTION

The Am79C973 and Am79C975 controllers are single-

chip 32-bit full- duplex, 10/100-Megabit per second

(Mbps) fully integrated PCI-to-Wire Fast Ethernet sys-

tem solution, designed to address high-performance

system application requirements. They are flexible bus

mastering device that can be used in any application,

including network-ready PCs and bridge/router de-

signs. The bus master architecture provides high data

throughput and low CPU and system bus utilization.

The Am79C973 and Am79C975 controllers are fabri-

cated with advanced low-power 3.3-V CMOS process

to provide low operating current for power sensitive ap-

plications.

The third generation Am79C973 and Am79C975 Fast

Ethernet controllers also have several enhancements

over t heir p r ed ecessor s, the Am79 C971 and

Am79C972 devices. Besides integrating the complete

10/100 Physical Layer (PHY) interface, they further re-

duce system implementation cost by integrating the

SRAM buffers on chip.

The Am79C973 and Am79C975 controllers contain 12-

kilobyte (Kbyte) buffers, the largest of their class in 10/

100 Mbps Ethernet controllers. The large internal buff-

ers are fully programmable between the RX and TX

queues for optimal performance.

The Am79C973 and Am79C975 controllers are also

compliant with PC98/PC99 and Wired for Management

specifications. They fully support Microsoft’s OnNow

and ACPI specifications, which are backward compati-

ble with Magic Packet technology and compliant with

the PCI Bus Power Management Interface Specifica-

tion by supporting the four power management states

(D0, D1, D2, and D3), the optional PME pin, and the

necessary configuration and data registers.

The Am79C973 and Am79C975 controllers are com-

plete Ethernet nodes integrated into a single VLSI de-

vice. It contains a bus interface unit, a Direct Memory

Access (DMA) Buffer Management Unit, an ISO/IEC

8802-3 (IEEE 802.3)- compliant Media Access Control-

ler (MAC), a large Transmit FIFO and a large Receive

FIFO, and an IEEE 802.3-compliant 10/100 Mbps PHY.

The integrated 10/100 PHY unit of the Am79C973 and

Am79C975 controllers implement the complete physi-

cal layer for 10BASE-T and the Physical Coding Sub-

layer (PCS), Physical Medium Attachment (PMA), and

Physical Medium Dependent (PMD) functionality for

100BASE-TX, including MLT-3 encoding/decoding. It

also supports 100BASE-FX operation by providing a

Pseudo-ECL (PECL) interface for direct connection to

a fiber optic transceiver module. The internal 10/100

PHY implements Auto-Negotiation for twisted-pair

(10T/100TX) operation by using a modified 10BASE-T

link integrity test pulse sequence as defined in the

IEEE 802.3u specification. The Auto-Negotiation func-

tion automatically configures the controller to operate

at the maximum performance level supported across

the network link.

The Am79C975 controller also implements a Serial

Management Interface in addition to the advanced

management features offered with the Am79C973 con-

troller. The Serial Management Interface is based on

the industry standard Inter-IC (I2C) and System Man-

agement Bus (SMBus) specifications and enables a

system to communicate with another network station

for remote monitoring and alerting of local system man-

agement parameters and events. This simple yet pow-

erful Serial Management Interface is capable of

communicating within the system and over the network

during normal operation or in low-power modes, even if

the device is not initialized or set up for transmit or re-

ceive operation by the network software driver.

The 32-bit multiplexed bus interface unit provides a di-

rect interface to the PCI local bus, simplifying the

design of an Ethernet node in a PC system. The

Am79C973 and Am79C975 controllers provide the

complete interface to an Expansion ROM or Flash de-

vice allowing add-on card designs with only a single

load per PCI bus interface pin. With their built-in sup-

port for both little and big endian byte alignment, the

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