AM79C973VCW datasheet(72/304 Pages) AMD

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Am79C973/Am79C975

P R E L I M INARY

See ANSI/IEEE Std 802.3-1993 Edition, 4.2.3.2.1:

Note: It is possible for the PLS carrier sense indication

to fail to be asserted during a collision on the media. If

the deference process simply times the inter-Frame

gap based on this indication, it is possible for a short

interFrame gap to be generated, leading to a potential

reception failure of a subsequent frame. To enhance

system robustness, the following optional measures,

as specified in 4.2.8, are recommended when Inter-

Frame-SpacingPart1 is other than 0:

1. Upon completing a transmission, start timing the in-

terrupted gap, as soon as transmitting and carrier

sense are both false.

2. When timing an inter-frame gap following reception,

reset the inter-frame gap timing if carrier sense be-

comes true during the first 2/3 of the inter-frame gap

timing interval. During the final 1/3 of the interval,

the timer shall not be reset to ensure fair access to

the medium. An initial period shorter than 2/3 of the

interval is permissible including 0.

The MAC engine implements the optional receive two

part deferral algorithm, with an InterFrameSpacing-

Part1 time of 6.0 ms. The InterFrameSpacingPart 2 in-

terval is, therefore, 3.4 ms.

The Am79C973/Am79C975 controller will perform the

two-part deferral algorithm as specified in Section 4.2.8

(Process Deference). The Inter Packet Gap (IPG) timer

will start timing the 9.6 ms InterFrameSpacing after the

receive carrier is deasserted. During the first part de-

fe r r al ( I n t er Fr a m eSpa cingPar t 1 - I F S 1 ) , the

Am79C973/Am79C975 controller will defer any pend-

ing transmit frame and respond to the receive mes-

sage. The IPG counter will be cleared to 0 continuously

until the carrier deasserts, at which point the IPG

counter will resume the 9.6 ms count once again. Once

the IFS1 period of 6.0 ms has elapsed, the Am79C973/

Am79C975 controller will begin timing the second part

deferral (InterFrameSpacingPart2 - IFS2) of 3.4 ms.

Once IFS1 has completed and IFS2 has commenced,

the Am79C973/Am79C975 controller will not defer to a

receive frame if a transmit frame is pending. This

means that the Am79C973/Am79C975 controller will

not attempt to receive the receive frame, since it will

start to transmit and generate a collision at 9.6 ms. The

Am79C973/Am79C975 controller will complete the

preamble (64-bit) and jam (32-bit) sequence before

ceasing transmission and invoking the random backoff

algorithm.

The Am79C973/Am79C975 controller allows the user

to program the IPG and the first part deferral (Inter-

Frame-SpacingPart1 - IFS1) through CSR125. By

changing the IPG default value of 96 bit times (60h), the

user can adjust the fairness or aggressiveness of the

Am79C973/Am79C975 MAC on the network. By pro-

gramming a lower number of bit times than the ISO/IEC

8802-3 standard requires, the Am79C973/Am79C975

MAC engine will become more aggressive on the net-

work. This aggressive nature will give rise to the

Am79C973/Am79C975 controller possibly capturing

the network at times by forcing other less aggressive

compliant nodes to defer. By programming a larger

number of bit times, the Am79C973/Am79C975 MAC

will become less aggressive on the network and may

defer more often than normal. The performance of the

Am79C973/Am79C975 controller may decrease as the

IPG value is increased from the default value, but the

resulting behavior may improve network performance

by reducing collisions. The Am79C973/Am79C975

controller uses the same IPG for back-to-back trans-

mits and receive-to-transmit accesses. Changing IFS1

will alter the per iod fo r wh ich the Am79C973/

Am79C975 MAC engine will defer to incoming receive

frames.

CAUTION: Care must be exercised when altering

these parameters. Adverse network activity could

result!

This transmit two-part deferral algorithm is imple-

mented as an option which can be disabled using the

DXMT2PD bit in CSR3. The IFS1 programming will

have no effect when DXMT2PD is set to 1, but the IPG

programming value is still valid. Two part deferral after

transmission is useful for ensuring that severe IPG

shrinkage cannot occur in specific circumstances,

causing a transmit message to follow a receive mes-

sage so closely as to make them indistinguishable.

During the time period immediately after a transmission

has been completed, the external transceiver should

generate the SQE Test message within 0.6 to 1.6 ms

after the transmission ceases. During the time period in

which the SQE Test message is expected, the

Am79C973/Am79C975 controller will not respond to

receive carrier sense.

See ANSI/IEEE Std 802.3-1993 Edition, 7.2.4.6 (1):

“At the conclusion of the output function, the DTE

opens a time window during which it expects to see

the signal_quality_error signal asserted on the

Control In circuit. The time window begins when

the

CARRIER_STATUS

becomes

CARRIER_OFF. If execution of the output function

does not cause CARRIER_ON to occur, no SQE

test occurs in the DTE. The duration of the window

shall be at least 4.0 ms but no more than 8.0 ms.

During the time window the Carrier Sense Function

is inhibited.”

The Am79C973/Am79C975 controller implements a

carrier sense “blinding” period of 4.0 ms length starting

from the deassertion of carrier sense after transmis-

sion. This effectively means that when transmit two part

deferral is enabled (DXMT2PD is cleared), the IFS1

time is from 4 ms to 6 ms after a transmission. How-

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