AM79C973VCW datasheet(13/304 Pages) AMD

13 / 304 page

Am79C973/Am79C975

P R E L I M INARY

Figure 1.

Slave Configuration Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 2.

Slave Configuration Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 3.

Slave Read Using I/O Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 4.

Slave Write Using Memory Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 5.

Expansion ROM Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 6.

Disconnect Of Slave Cycle When Busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 7.

Disconnect Of Slave Burst Transfer - No Host Wait States . . . . . . . . . . . . . 44

Figure 8.

Disconnect Of Slave Burst Transfer - Host Inserts Wait States . . . . . . . . . . 45

Figure 9.

Address Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 10. Slave Cycle Data Parity Error Response 46

Figure 11. Bus Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 12. Non-Burst Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 13. Burst Read Transfer (EXTREQ = 0, MEMCMD = 0) . . . . . . . . . . . . . . . . . . 48

Figure 14. Non-Burst Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 15. Burst Write Transfer (EXTREQ = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 16. Disconnect With Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 17. Disconnect Without Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 18. Target Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 19. Preemption During Non-Burst Transaction . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 20. Preemption During Burst Transaction

Figure 21. Master Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 22. Master Cycle Data Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 23. Initialization Block Read In Non-Burst Mode

Figure 24. Initialization Block Read In Burst Mode

Figure 25. Descriptor Ring Read In Non-Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 26. Descriptor Ring Read In Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 27. Descriptor Ring Write In Non-Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 28. Descriptor Ring Write In Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 29. FIFO Burst Write At Start Of Unaligned Buffer . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 30. FIFO Burst Write At End Of Unaligned Buffer . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 31. 16-Bit Software Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 32. 32-Bit Software Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 33. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 34. IEEE 802.3 Frame And Length Field Transmission Order . . . . . . . . . . . . . . 77

Figure 35. 100BASE-X Transmit and Receive Data Paths of the Internal PHY . . . . . . 81

Figure 36. MLT-3 Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 37. TX± and RX± Termination 86

Figure 38. 10BASE-T Transmit and Receive Data Paths . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 39. Receive Frame Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 40. Flash Configuration for the Expansion Bus . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 41. EPROM Only Configuration for the Expansion Bus (64K EPROM) . . . . . . . 92

Figure 42. EPROM Only Configuration for the Expansion Bus (64K EPROM)

Figure 43. Expansion ROM Bus Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 44. Flash Read from Expansion Bus Data Port . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 45. Flash Write from Expansion Bus Data Port . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 46. Block Diagram No SRAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 47. Block Diagram Low Latency Receive Configuration . . . . . . . . . . . . . . . . . . 97

Figure 48. LED Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

LIST OF FIGURES

AM79C973VCW 数据表(PDF) 13 Page - Advanced Micro Devices

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