AM79C973VCW datasheet(46/304 Pages) AMD

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Am79C973/Am79C975

P R E L I M INARY

Figure 10. Slave Cycle Data Parity Error Response

Master Bus Interface Unit

The master Bus Interface Unit (BIU) controls the acqui-

sition of the PCI bus and all accesses to the initializa-

tion block, descriptor rings, and the receive and

transmit buffer memory. Table 4 shows the usage of

PCI commands by the Am79C973/Am79C975 control-

ler in master mode.

Bus Acquisition

The Am79C973/Am79C975 microcode will determine

when a DMA transfer should be initiated. The first step

in any Am79C973/Am79C975 bus master transfer is to

acquire ownership of the bus. This task is handled by

synchronous logic within the BIU. Bus ownership is re-

quested with the REQ signal and ownership is granted

by the arbiter through the GNT signal.

Figure 11 shows the Am79C973/Am79C975 controller

bus acquisition. REQ is asserted and the arbiter re-

turns GNT while another bus master is transferring

data. The Am79C973/Am79C975 controller waits until

the bus is idle (FRAME and IRDY deasserted) before it

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

PAR

ADDR

CMD

PAR

2345678

DATA

PAR

PERR

21510D-15

Table 4. Master Commands

C[3:0]

Command

Use

0000

Interrupt

Acknowledge

Not used

0001

Special Cycle

Not used

0010

I/O Read

Not used

0011

I/O Write

Not used

0100

Reserved

0101

Reserved

0110

Memory Read

Read of the initialization

block and descriptor

rings

Read of the transmit

buffer in non-burst mode

0111

Memory Write

Write to the descriptor

rings and to the receive

buffer

1000

Reserved

C[3:0]

Command

Use

1001

Reserved

1010

Configuration Read

Not used

1011

Configuration Write

Not used

1100

Memory Read

Multiple

Read of the transmit

buffer in burst mode

1101

Dual Address Cycle Not used

1110

Memory Read Line

Read of the transmit

buffer in burst mode

1111

Memory Write

Invalidate

Not used

Table 4. Master Commands (Continued)

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