AM79C973VCW datasheet(3/304 Pages) AMD

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Am79C973/Am79C975

P R E L I M INARY

controllers also address non-PC applications. The

Am79C973 and Am79C975 controllers’ advanced

CMOS design allows the bus interface to be connected

to either a +5-V or a +3.3-V signaling environment. A

compliant IEEE 1149.1 JTAG test interface for board-

level testing is also provided, as well as a NAND tree

test structure for those systems that cannot support the

JTAG interface.

The Am79C973 and Am79C975 controllers support

auto-configuration in the PCI configuration space. Ad-

ditional Am79C973 and Am79C975 controller configu-

ration parameters, including the unique IEEE physical

address, can be read from an external non-volatile

memory (EEPROM) immediately following system re-

set.

In addition, the Am79C973 and Am79C975 controllers

provide programmable on-chip LED drivers for trans-

mit, receive, collision, link integrity, Magic Packet sta-

tus, activity, link active, address match, full-duplex, 10

Mbps or 100 Mbps, or jabber status.

The Am79C973 and Am79C975 controllers are regis-

ter compatible with the LANCE™ (Am7990) Ethernet

controller, the C-LANCE™ (Am79C90) Ethernet con-

troller, and all Ethernet controllers in the PCnet™ Fam-

ily, except ILACC™ (Am79C900), including the PCnet-

ISA™ (Am79C960), PCnet-ISA+™ (Am79C961),

PC net - I SA II ™ ( A m7 9C9 61A) , PCne t- 32 ™

( A m79 C 96 5) ,

PCne t- PCI ™

( A m 79C 970) ,

PCnet-PCI II ™ (A m79C970A ), P Cnet- FAST ™

(Am79C971), and PCnet-FAST+™ (Am79C972). The

Buffer Management Unit supports the LANCE and

PCnet descriptor software models.

The Am79C973 and Am79C975 controllers are ideally

suited for LAN on the motherboard, network adapter

card, and embedded designs. It is available in a 160-

pin Plastic Quad Flat Pack (PQFP) package and also in

a 176-pin Thin Quad Flat Pack (TQFP) package for

form factor sensitive designs.

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