STM32F103RG datasheet(16/120 Pages) STMICROELECTRONICS

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Description

STM32F103xF, STM32F103xG

16/120

Doc ID 16554 Rev 3

2.3.5

Embedded SRAM

96 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.

2.3.6

FSMC (flexible static memory controller)

The FSMC is embedded in the STM32F103xF and STM32F103xG performance line family.

It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash,

SRAM, PSRAM, NOR and NAND.

Functionality overview:

●

The three FSMC interrupt lines are ORed in order to be connected to the NVIC

●

Write FIFO

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Code execution from external memory except for NAND Flash and PC Card

●

The targeted frequency, fCLK, is HCLK/2, so external access is at 36 MHz when HCLK

is at 72 MHz and external access is at 24 MHz when HCLK is at 48 MHz

2.3.7

LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It

supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to

specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-

effective graphic applications using LCD modules with embedded controllers or high-

performance solutions using external controllers with dedicated acceleration.

2.3.8

Nested vectored interrupt controller (NVIC)

The STM32F103xF and STM32F103xG performance line embeds a nested vectored

interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16

interrupt lines of Cortex™-M3) and 16 priority levels.

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Closely coupled NVIC gives low latency interrupt processing

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Interrupt entry vector table address passed directly to the core

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Closely coupled NVIC core interface

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Allows early processing of interrupts

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Processing of late arriving higher priority interrupts

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Support for tail-chaining

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Processor state automatically saved

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Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

2.3.9

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected

to the 16 external interrupt lines.

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