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STM32F217VG 数据表(PDF) 115 Page - STMicroelectronics |
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STM32F217VG 数据表(HTML) 115 Page - STMicroelectronics |
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115 / 173 page  STM32F21xxx Electrical characteristics Doc ID 17050 Rev 8 115/173 Equation 1: RAIN max formula The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. a fS (2) Sampling rate (fADC = 30 MHz) 12-bit resolution Single ADC -- 2 Msps 12-bit resolution Interleave Dual ADC mode - - 3.75 Msps 12-bit resolution Interleave Triple ADC mode -- 6 Msps IVREF+ (2) ADC VREF DC current consumption in conversion mode fADC = 30 MHz 3 sampling time 12-bit resolution - 300 500 µA fADC = 30 MHz 480 sampling time 12-bit resolution -- 16 µA IVDDA (2) ADC VDDA DC current consumption in conversion mode fADC = 30 MHz 3 sampling time 12-bit resolution -1.6 1.8 mA fADC = 30 MHz 480 sampling time 12-bit resolution -- 60 µA 1. It is recommended to maintain the voltage difference between VREF+ and VDDA below 1.8 V. 2. Based on characterization, not tested in production. 3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 4. RADC maximum value is given for VDD=1.8 V, and minimum value for VDD=3.3 V. 5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 63. Table 63. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit Table 64. ADC accuracy (1) Symbol Parameter Test conditions Typ Max(2) Unit ET Total unadjusted error fPCLK2 = 60 MHz, fADC = 30 MHz, RAIN < 10 kΩ, VDDA = 1.8 to 3.6 V ±2 ±5 LSB EO Offset error ±1.5 ±2.5 EG Gain error ±1.5 ±3 ED Differential linearity error ±1 ±2 EL Integral linearity error ±1.5 ±3 RAIN k0.5 – () fADC CADC 2 N 2 + () ln × × -------------------------------------------------------------- RADC – = |
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