STM32F217VG datasheet(20/173 Pages) STMICROELECTRONICS

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Description

STM32F21xxx

20/173

Doc ID 17050 Rev 8

2.2.10

Nested vectored interrupt controller (NVIC)

The STM32F21x devices embed a nested vectored interrupt controller able to manage 16

priority levels, and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of

the Cortex™-M3.

The NVIC main features are the following:

●

Closely coupled NVIC gives low-latency interrupt processing

●

Interrupt entry vector table address passed directly to the core

●

Closely coupled NVIC core interface

●

Allows early processing of interrupts

●

Processing of late arriving, higher-priority interrupts

●

Support tail chaining

●

Processor state automatically saved

●

Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimum interrupt

latency.

2.2.11

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 23 edge-detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected

to the 16 external interrupt lines.

2.2.12

Clocks and startup

On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The

16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application can

then select as system clock either the RC oscillator or an external 4-26 MHz clock source.

This clock is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator and a software interrupt is generated (if enabled). Similarly,

full interrupt management of the PLL clock entry is available when necessary (for example if

an indirectly used external oscillator fails).

The advanced clock controller clocks the core and all peripherals using a single crystal or

oscillator. In particular, the ethernet and USB OTG FS peripherals can be clocked by the

system clock.

Several prescalers and PLLs allow the configuration of the three AHB buses, the high-speed

APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three

AHB buses is 120 MHz and the maximum frequency the high-speed APB domains is

60 MHz. The maximum allowed frequency of the low-speed APB domain is 30 MHz.

The devices embed a dedicate PLL (PLLI2S) which allow to achieve audio class

performance. In this case, the I2S master clock can generate all standard sampling

frequencies from 8 kHz to 192 kHz.

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