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STM32F217VG 数据表(PDF) 131 Page - STMicroelectronics

部件名 STM32F217VG
功能描述  ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/1284KB RAM
PDF  173 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32F217VG 数据表(HTML) 131 Page - STMicroelectronics

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STM32F21xxx
Electrical characteristics
Doc ID 17050 Rev 8
131/173
Figure 60.
Synchronous non-multiplexed PSRAM write timings
Table 76.
Synchronous non-multiplexed PSRAM write timings(1)(2)
1.
CL = 30 pF.
2.
Based on characterization, not tested in production.
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FSMC_CLK period
2THCLK- 1
-
ns
td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2)
-
1
ns
td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2)
1
-
ns
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low
-
5
ns
td(CLKL-
NADVH)
FSMC_CLK low to FSMC_NADV high
6
-
ns
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x=16…25)
-
0
ns
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x=16…25)
8
-
ns
td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low
-
1
ns
td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high
1
-
ns
td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low
-
2
ns
td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high
2
-
ns
FSMC_CLK
FSMC_NEx
FSMC_A[25:0]
FSMC_NWE
FSMC_D[15:0]
D1
D2
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
tw(CLK)
tw(CLK)
Data latency = 0
BUSTURN = 0
td(CLKL-NExL)
td(CLKL-NExH)
td(CLKL-AV)
td(CLKL-AIV)
td(CLKL-NWEH)
td(CLKL-NWEL)
td(CLKL-Data)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
ai14993g
FSMC_NADV
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-Data)
FSMC_NBL
td(CLKL-NBLH)



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