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STM32F207IE 数据表(PDF) 21 Page - STMicroelectronics

部件名 STM32F207IE
功能描述  ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/1284KB RAM
PDF  178 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32F207IE 数据表(HTML) 21 Page - STMicroelectronics

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STM32F20xxx
Functional overview
177
The DMA can be used with the main peripherals:
SPI and I2S
I2C
USART and UART
General-purpose, basic and advanced-control timers TIMx
DAC
SDIO
Camera interface (DCMI)
ADC.
3.9
Flexible static memory controller (FSMC)
The FSMC is embedded in all STM32F20x devices. It has four Chip Select outputs
supporting the following modes: PC Card/Compact Flash, SRAM, PSRAM, NOR Flash and
NAND Flash.
Functionality overview:
Write FIFO
Code execution from external memory except for NAND Flash and PC Card
Maximum frequency (fHCLK) for external access is 60 MHz
LCD parallel interface
The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
3.10
Nested vectored interrupt controller (NVIC)
The STM32F20x devices embed a nested vectored interrupt controller able to manage 16
priority levels, and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of
the Cortex™-M3.
The NVIC main features are the following:
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support tail chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.



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