STM32F207IE datasheet(23/178 Pages) STMICROELECTRONICS

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STM32F20xxx

Functional overview

177

in the 0 to 70 °C temperature range using an external power supply supervisor (see

Section 3.16).

•

VSSA, VDDA = 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset

blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.

•

VBAT = 1.65 to 3.6 V: power supply for RTC, external clock, 32 kHz oscillator and

backup registers (through power switch) when VDD is not present.

Refer to Figure 19: Power supply scheme for more details.

3.15

Power supply supervisor

The devices have an integrated power-on reset (POR) / power-down reset (PDR) circuitry

coupled with a Brownout reset (BOR) circuitry.

At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V.

After the 1.8 V POR threshold level is reached, the option byte loading process starts, either

to confirm or modify default BOR threshold levels, or to disable BOR permanently. Three

BOR thresholds are available through option bytes.

The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or

VBOR, without the need for an external reset circuit. On devices in WLCSP64+2 package,

the BOR, POR and PDR features can be disabled by setting IRROFF pin to VDD. In this

mode an external power supply supervisor is required (see Section 3.16).

The devices also feature an embedded programmable voltage detector (PVD) that monitors

the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be

generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is

higher than the VPVD threshold. The interrupt service routine can then generate a warning

message and/or put the MCU into a safe state. The PVD is enabled by software.

3.16

Voltage regulator

The regulator has five operating modes:

•

Regulator ON

–

Main regulator mode (MR)

–

Low power regulator (LPR)

–

Power-down

•

Regulator OFF

–

Regulator OFF/internal reset ON

–

Regulator OFF/internal reset OFF

3.16.1

Regulator ON

The regulator ON modes are activated by default on LQFP packages.On WLCSP64+2

package, they are activated by connecting both REGOFF and IRROFF pins to VSS, while

only REGOFF must be connected to VSS on UFBGA176 package (IRROFF is not available).

VDD minimum value is 1.8 V.

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