STM32F415VG datasheet(25/186 Pages) STMICROELECTRONICS

25 / 186 page

DocID022063 Rev 4

25/186

STM32F415xx, STM32F417xx

Description

The VDD specified threshold, below which the device must be maintained under reset, is

1.8 V (see Figure 7). This supply voltage can drop to 1.7 V when the device operates in the

0 to 70 °C temperature range.

A comprehensive set of power-saving mode allows to design low-power applications.

When the internal reset is OFF, the following integrated features are no more supported:

•

The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled

•

The brownout reset (BOR) circuitry is disabled

•

The embedded programmable voltage detector (PVD) is disabled

•

VBAT functionality is no more available and VBAT pin should be connected to VDD

All packages, except for the LQFP64 and LQFP100, allow to disable the internal reset

through the PDR_ON signal.

Figure 8. PDR_ON and NRST control with internal reset OFF

1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range.

2.2.16

Voltage regulator

The regulator has four operating modes:

•

Regulator ON

–

Main regulator mode (MR)

–

Low power regulator (LPR)

–

Power-down

•

Regulator OFF

Regulator ON

On packages embedding the BYPASS_REG pin, the regulator is enabled by holding

BYPASS_REG low. On all other packages, the regulator is always enabled.

MS19009V6

V DD

time

PDR = 1.7 V or 1.8 V

(1)

time

NRST

PDR_ON

Reset by other source than

power supply supervisor

STM32F415VG 数据表(PDF) 25 Page - STMicroelectronics

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