STM32F415VG datasheet(26/186 Pages) STMICROELECTRONICS

26 / 186 page

Description

STM32F415xx, STM32F417xx

26/186

DocID022063 Rev 4

There are three power modes configured by software when regulator is ON:

•

MR is used in the nominal regulation mode (With different voltage scaling in Run)

In Main regulator mode (MR mode), different voltage scaling are provided to reach the

best compromise between maximum frequency and dynamic power consumption.

Refer to Table 14: General operating conditions.

•

LPR is used in the Stop modes

The LP regulator mode is configured by software when entering Stop mode.

•

Power-down is used in Standby mode.

The Power-down mode is activated only when entering in Standby mode. The regulator

output is in high impedance and the kernel circuitry is powered down, inducing zero

consumption. The contents of the registers and SRAM are lost)

Two external ceramic capacitors should be connected on VCAP_1 & VCAP_2 pin. Refer to

Figure 21: Power supply scheme and Figure 16: VCAP_1/VCAP_2 operating conditions.

All packages have regulator ON feature.

Regulator OFF

This feature is available only on packages featuring the BYPASS_REG pin. The regulator is

disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply

externally a V

12 voltage source through V

CAP_1 and VCAP_2 pins.

Since the internal voltage scaling is not manage internally, the external voltage value must

be aligned with the targetted maximum frequency. Refer to Table 14: General operating

conditions.

The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling

capacitors.

Refer to Figure 21: Power supply scheme

When the regulator is OFF, there is no more internal monitoring on V

12. An external power

supply supervisor should be used to monitor the V

12 of the logic power domain. PA0 pin

should be used for this purpose, and act as power-on reset on V

12 power domain.

In regulator OFF mode the following features are no more supported:

•

PA0 cannot be used as a GPIO pin since it allows to reset a part of the V

12 logic power

domain which is not reset by the NRST pin.

•

As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As

a consequence, PA0 and NRST pins must be managed separately if the debug

connection under reset or pre-reset is required.

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