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AS8501 数据表(PDF) 30 Page - ams AG

部件名 AS8501
功能描述  High precision voltage and current measurement sensor interface
PDF  41 Pages
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制造商  AMSCO [ams AG]
网页  http://www.ams.com
标志 AMSCO - ams AG

AS8501 数据表(HTML) 30 Page - ams AG

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AS8501 - Data Sheet
austriamicrosystems
Revision 1.1, 04-April-06
www.austriamicrosystems.com
Page 29 of 40
SDI bus timing
Nr.
PARAMETER
SYMBOL
MIN
TYP
MAX
Unit
Conditions
NOTE
0
SCLK pulse width
PW_sclk
120
ns
All
1
SCLK low
LO_sclk
120
ns
All
5), 6)
2
Master SDAT exception
after SCLK
MDE
120
ns
All
3
Master SDAT valid
before/after SCLK
DV_m
120
TSW
ns
All
1)
4
Slave SDAT not valid
after SCLK
DV_s
120
ns
Master read
5
Master 3-state ON/OFF
TS_m
TS_s
TSW
ns
Master read
6
Slave 3-state ON/OFF
TS_s
120
ns
Master read
7
Bus condition detection
disabled in slave unit
CDD
ns
Master read 3)
Notes:
1)
TSW is typical time required by the microcontroller program to change or to read the state of
the I/O pin
3)
Start detection is disabled when slave unit transmits data
5)
LO_sclk>300ns and PW_sclk> 2µsec required to read ZZR.
6)
LO_sclk > (3/2)*TCLK = (3/2)/f CLK = (3/2)/8MHz=187.5ns required for results synchronisation in MSR.
8.6
SDI access to OTP memory
SDI can read the OTP memory in any mode by reading the register ZZR.
8.6.1
ZZR register bit mapping
Cell index
0
1
2
3
4
5
6
7
Purpose
pos A 1)
pos B 2)
pos C 3)
lock A 4)
lock B 5)
trimcs
trimc3
trimc2
ZZR field
ZLO
ZLO
ZLO
ZLO
ZLO
ZTR
ZTR
ZTR
ZZR bit
187 (msb)
186
185
184
183
182
181
180
1)
Always programmed to '0' during the production test
2)
Always programmed to '0' during the production test
3)
Always programmed to '1' during the production test
4)
Reserved
5)
Reserved



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