CS5321 datasheet(24/38 Pages) CIRRUS

24 / 38 page

CS5320/21/22

DS454PP1

To avoid possible high current states while in the

power down state, the following conditions apply:

1) CLKIN must be active for at least 64 clock cy-

cles after PWDN entry.

2) CSEL and TDATA must not both be asserted

high.

2.13 SYNC Operation

The SYNC pin is used to start convolutions and

synchronize the CS5322 and CS5320/21 to an ex-

ternal sampling source or timing reference. The

SYNC event is recognized on the first CLKIN ris-

ing edge after the SYNC pin goes high. SYNC may

remain high indefinitely. Only the sequence of

SYNC rising followed by CLKIN rising generates

a SYNC event.

The SYNC event aligns the output sample and

causes the filter to begin convolutions. The first

SYNC event causes an immediate DRDY provided

DRDY is low. Subsequent data ready events will

occur at a rate determined by the decimation rate

inputs DECC, DECB, and DECA. Multiple SYNC

events can be applied with no effect on operation if

they are perfectly timed according to the decima-

tion rate. Any SYNC event not in step with the dec-

imation rate will cause a realignment and loss of

data.

2.14 Serial Read Operation

Serial read is used to obtain status or conversion

data. The CS, R/W, SCLK, RSEL, and SOD pins

control the read operation. The serial read opera-

tion is activated when CS goes low (CS=0) with the

R/W pin high (R/W=1). The RSEL pin selects be-

tween conversion data (data register) or status in-

formation (status register). The selected serial bit

stream is output on the SOD (Serial Output Data)

pin.

On read select, SCLK can either be high or low, the

first bit appears on the SOD pin and should be

latched on the falling edge of SCLK. After the first

SCLK falling edge, each SCLK rising edge shifts

out a new bit. Status reads are 16 bits, and data

reads are 24 bits. Both streams are supplied as MSB

first, LSB last.

In the event more SCLK pulses are supplied than

necessary to clock out the requested information,

trailing zeroes will be output for data reads and

trailing LSB’s for status reads. If the read operation

is terminated before all the bits are read, the inter-

nal bit pointer is reset to the MSB so that a re-read

will give the same data as the first read, with one

exception. The status error flags are cleared on read

and will not be available on a re-read.

The status error flags must be read before entering

the power-down state. If an error has occurred be-

fore entering powerdown and the status bit (ER-

ROR) has not been read, the status bits (ER-ROR,

OVERWRITE, MFLG, ACC1 and ACC2) may not

be cleared on status reads. Upon exiting the power-

down state and entering normal operation, the user

may be flagged that an error is still present.

The SOD pin floats when read operation is deacti-

vated (R/W=1, CS=1). This enables the SID and

SOD pins to be tied together to form a bi-direction-

al serial data bus. There is an internal nominal

100 k

Ω pull-up resistor on the SOD pin.

2.15 Serial Write Operation

Serial write is used to write data to the configura-

tion register. The CS, R/W, SCLK and SID pins

control the serial write operation. The serial write

operation is activated when CS goes low (CS=0)

with R/W pin low (R/W=0).

Serial input data on the SID pin is sampled on the

falling edge of SCLK. The input bits are stored in a

temporary buffer until either the write operation is

terminated or 8 bits have been received. The data is

then parallel loaded into the configuration register.

If fewer than 8 bits are input before the write termi-

nation, the other bits may be indeterminate.

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