CS5321 datasheet(27/38 Pages) CIRRUS

27 / 38 page

CS5320/21/22

DS454PP1

present. In normal operation the ACC1 error will

only occur when the input data stream to FIR1 is all

1’s for more than 32 bits. The ACC2 error cannot

occur in normal operation.

The DRDY bit reflects the state of the DRDY pin.

DRDY rising edge indicates that a new data word

has been loaded into the data register and is avail-

able for reading. DRDY will fall after the SCLK

falling edge that reads the data register LSB. If no-

data read attempt is made, DRDY will pulse low

for 1/2 CLKIN cycle, providing a positive edge on

the new data availability. In the OVERWRITE

case, DRDY remains high because new data is not

loaded at the normal end of conversion time.

The 1SYNC status bit provides an indication of the

filter group delay. It goes high on the second output

sample after SYNC and is valid for only that sam-

ple. For repetitive SYNC operations, SYNC must

run at one fourth the output word rate or slower to

avoid interfering with the 1SYNC operation. With

these slower repetitive SYNC’s or non-periodic

SYNC’s separated by at least three output words,

1SYNC will occur on the second output sample af-

ter SYNC.

ORCALD indicates that calibration of the offset

able in the output register. This flag is high only

during that sample and is otherwise low.

The remaining five status bits (PWDN, ORCAL,

USEOR, CSEL, Reserved, DECC, DECB, and DE-

CA) provide configuration readback for the user.

These bits echo the control source for the CS5322

such that in the hardware mode (H/S=1), they fol-

low the corresponding input pins. In host mode

(H/S=0) they follow the corresponding configura-

tion bits.

A brief explanation of the eight bits are as follows:

PWDN - When high, indicates that the CS5322 is in

the power-down state.

ORCAL - When high, indicates a potential calibra-

tion start.

USEOR - When high, indicates the Offset Register is

used. During calibration, this bit will read zero indi-

cating the offset register is not being used during cal-

ibration.

CSEL- When high, TDATA is selected as the filter

source. When low, the MDATA output signal from

the CS5320/21 is selected as the input source to the

filter.

Reserved - Always read low.

DECC, DECB, and DECA - Indicate the decimation

rate of the filter and are defined in Table 4.

DECC

DECB

DECA

Output Word Rate (Hz)

Clocks Filter Output

62.5

16384

125

8192

250

4096

500

2048

1000

1024

2000

512

4000

256

Reserved

Table 4. Bandwidth Selection: Truth Table

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