CS5321 datasheet(26/38 Pages) CIRRUS

26 / 38 page

CS5320/21/22

DS454PP1

2.17 Status Bits

The Status Register is a 16-bit register which al-

lows the user to read the flags and configuration

settings of the CS5322. Table 3 documents the data

bits of the Status Register.

The ERROR flag, ERROR, is the OR’ed result of

OVERWRITE, MFLG, ACC1, and ACC2. The

ERROR bit is active high whenever any of the four

error bits are set due to a fault condition. The ER-

ROR output has a nominal 100 K

Ω internal pull-up

resistor.

The OVERWRITE bit is set when new conversion

data is ready to be loaded into the data register, but

the previous data was not completely read out. This

can occur on either of two conditions: a read oper-

ation is in progress or a read operation was started,

then aborted, and not completed. These two condi-

tions are data read attempts. The attempt is identi-

fied by the first SCLK low edge (MSB read) of a

data register read. If a data register read is not at-

tempted, the CS5322 assumes that data is not want-

ed and does not assert OVERWRITE, and the old

data is over-written by the new data. On an OVER-

WRITE condition, the old partially read data is pre-

served, and the new data word is lost.

Status reads have no effect on OVERWRITE assert

operations. The OVERWRITE bit is cleared on a

status register read or RESET.

The MFLG error bit reflects the CS5320/21 MFLG

signal. Any high level on the CS5322 MFLG pin

will set the MFLG status bit. The bit is cleared on a

status register read or RESET operation, only if the

MFLG pin on the CS5322 has returned low. A in-

ternal nominal 100 K

Ω pulldown resistor is on the

MFLG pin.

The accumulator error bits, ACC1 and ACC2, indi-

cate that an underflow or overflow has occurred in

the FIR1 filter for ACC1, or the FIR2 and FIR3 fil-

ters for ACC2. Both errors are cleared on a status

read, provided the error conditions are no longer

Output Bit #

Function

Description

1 (MSB)

Error

Detects one of the errors below

OVERWRITE Error

Overwrite Error

MFLG Error

Modulator Flag Error

ACC1 Error

Accumulator 1 Error

ACC2 Error

Accumulator Error

DRDY

Data Ready

1SYNC

First sample after SYNC

ORCALD

Offset calibration done

PWDN

Standby mode

ORCAL

Self-offset Calibration

USEOR

Use Offset Register

CSEL

Channel Select

Reserved

Factory use only

DECC

Bandwidth Selection Status

DECB

Bandwidth Selection Status

DECA

Bandwidth Selection Status

Table 3. Status Data (from the SOD Pin)

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