CS5320/21/22

30

DS454PP1

AINR - Analog Input Rough, PIN 10

Allows a non-linear current to bypass the main external anti-aliasing filter which if allowed to

happen, would cause harmonic distortion in the modulator. Please refer to the System

Connection Diagram and the Analog Input and Voltage Reference section of the data sheet for

recommended use of this pin.

VREF+ – Positive Voltage Reference Input, PIN 5

This pin accepts an external +4.5 V voltage reference.

VREF- – Negative Voltage Reference Input, PIN 6

This pin is tied to ground.

Digital Inputs

MCLK – Clock Input, PIN 20

A CMOS-compatible clock input to this pin (nominally 1.024 MHz) provides the necessary

clock for operation of the modulator and data output portions of the A/D converter. MCLK is

normally supplied by the CS5322

MSYNC – Modulator Sync, PIN 25

A transition from a low to high level on this input will re-initialize the CS5320/21. MSYNC

resets a divider-counter to align the MDATA output bit stream from the CS5320/21 with the

timing inside the CS5322.

OFST - Offset, PIN 28

When high, adds approximately 100 mV of input referred offset to guarantee that any zero

input limit cycles are out of band if present. When low, zero offset is added.

LPWR - Low Power Mode, PIN 27

The CS5320/21 power dissipation can be reduced from its nominal value of 55 mW to 30 mW

under the following conditions:

LPWR=1; MCLK = 512 kHz, HBR=1; or LPWR=1; MCLK = 1.024 MHz, HBR=0

HBR – High Bit Rate, Pin 26

Digital Outputs

MDATA – Modulator Data Output, PIN 18

Data will be presented in a one-bit serial data stream at a bit rate of 256 kHz (HBR=1) or

128 kHz (HBR=0) with MCLK operating at 1.024 MHz.

MDATA – Modulator Data Output, PIN 17

Inverse of the MDATA output.

MFLG – Modulator Flag, PIN 24

A transition from a low to high level signals that the CS5320/21 modulator is unstable due to

an over-range on the analog input