CS5320/21/22

DS454PP1

31

4. CS5322 PIN DESCRIPTIONS

Power Supplies

VD+ – Positive Digital Power, Pin 8, 21

Positive digital supply voltage. Nominally +5 volts.

DGND – Digital Ground, Pin 9, 20

Digital ground reference.

Digital Outputs

MCLK – Modulator Clock Output, Pin 7

A CMOS-compatible clock output (nominally 1.024 MHz) that provides the necessary clock for

operation of the modulator.

MSYNC – Modulator Sync, Pin 5

The transition from a low to high level on this output will re-initialize the CS5320/21.

ERROR - Error Flag, Pin 23

This signal is the output of an open pull-up NOR gate with a nominal 100 k

Ω pull-up resistor

to which the error status data (OVERWRITE error, MFLG error, ACC1 error and ACC2 error)

are inputs. When low, it notifies the host processor that an error condition exists. The ERROR

signal can be wire OR’d together with other filters’ outputs. The value of the internal pull-up

resistor is 100 k

Ω.

DRDY - Data Ready, Pin 22

When high, data is ready to be shifted out of the serial port data register.

TOP

VIEW

22

20

24

19

21

23

25

327

2

42 6

28

1

12

14

16

18

13

15

17

8

6

10

5

7

9

11

CHIP SELECT

CS

FRAME SYNC

SYNC

R/W

READ/WRITE

CLOCK INPUT

CLKIN

RSEL

REGISTER SELECT

RESET RESET

SCLK

SERIAL CLOCK

MODULATOR SYNC MSYNC

SID

SERIAL INPUT DATA

MODULATOR FLAG

MFLG

SOD

SERIAL OUTPUT DATA

MODULATOR CLOCK

MCLK

CS5322

ERROR ERROR FLAG

POSITIVE DIGITAL POWER

VD+

DRDY

DATA READY

DIGITAL GROUND

DGND

VD+

POSITIVE DIGITAL POWER

MODULATOR DATA MDATA

DGND

DIGITAL GROUND

TEST DATA TDATA

ORCAL OFFSET CALIBRATION

CHANNEL SELECT

CSEL

DECA

DECIMATION RATE CONTROL

HARDWARE/SOFTWARE MODE

H/S

DECIMATION RATE CONTROL

POWER DOWN PWDN

DECB

DECC

DECIMATION RATE CONTROL

USEOR USE OFFSET REGISTER