DS80C310

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DUAL DATA POINTER

Data memory block moves can be accelerated using the DS80C310 Dual Data Pointer (DPTR). The

standard 8032 DPTR is a 16-bit value that is used to address off-chip data RAM or peripherals. In the

DS80C310, the standard data pointer is called DPTR and is located at SFR addresses 82h and 83h. These

are the standard locations. No modification of standard code is needed to use DPTR. The new DPTR is

located at SFR 84h and 85h and is called DPTR1. The DPTR Select bit (DPS) chooses the active pointer

and is located at the lsb of the SFR location 86h. No other bits in register 86h have any effect and are set

to 0. The user switches between data pointers by toggling the lsb of register 86h. The increment (INC)

instruction is the fastest way to accomplish this. All DPTR-related instructions use the currently selected

DPTR for any activity. Therefore only one instruction is required to switch from a source to a destination

address. Using the Dual Data Pointer saves code from needing to save source and destination addresses

when doing a block move. Once loaded, the software simply switches between DPTR0 and 1. The

relevant register locations are as follows.

DPL

82h

Low byte original DPTR

DPH

83h

High byte original DPTR

DPL1

84h

Low byte new DPTR

DPH1

85h

High byte new DPTR

DPS

86h

DPTR Select (lsb)

STOP MODE ENHANCEMENTS

Setting bit 1 of the Power Control register (PCON; 87h) invokes the Stop mode. Stop mode is the lowest

µA

(but is specified in the Electrical Specifications). The CPU will exit Stop mode from an external interrupt

or a reset condition. Internally generated interrupts are not useful since they require clocking activity.

The DS80C310 allows a resume from Stop using an INT2-5, which are edge-triggered interrupts. The

start-up timing is managed by an internal crystal counter. A delay of 65,536 clocks occurs to give the

crystal enough time to start and stabilize.

PERIPHERAL OVERVIEW

The DS80C310 provides the same peripheral functions as the standard 80C32. It is compatible with the

DS80C320 but does not offer all of the peripherals.

TIMER RATE CONTROL

There is one important difference between the DS80C310 and 8051 regarding timers. The original 8051

used 12 clocks per cycle for timers as well as for machine cycles. The DS80C310 architecture normally

uses 4 clocks per machine cycle. However, in the area of timers and serial ports, the DS80C310 will

default to 12 clocks per cycle on reset. This allows existing code with real-time dependencies such as

baud rates to operate properly.

If an application needs higher speed timers or serial baud rates, the user can select individual timers to run

at the 4-clock rate. The Clock Control register (CKCON; 8Eh) determines these timer speeds. When the

relevant CKCON bit is a logic 1, the DS80C310 uses 4 clocks per cycle to generate timer speeds. When

the bit is a 0, the DS80C310 uses 12 clocks for timer speeds. The reset condition is a 0. CKCON.5 selects

the speed of Timer 2. CKCON.4 selects Timer 1 and CKCON.3 selects Timer 0. Note that unless a user

desires very fast timing, it is unnecessary to alter these bits. Note that the timer controls are independent.