数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

DS80C310 数据表(PDF) 15 Page - Dallas Semiconductor

部件名 DS80C310
功能描述  High-Speed Micro
PDF  23 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  DALLAS [Dallas Semiconductor]
网页  https://www.maximintegrated.com/en.html
标志 DALLAS - Dallas Semiconductor

DS80C310 数据表(HTML) 15 Page - Dallas Semiconductor

Back Button DS80C310 Datasheet HTML 11Page - Dallas Semiconductor DS80C310 Datasheet HTML 12Page - Dallas Semiconductor DS80C310 Datasheet HTML 13Page - Dallas Semiconductor DS80C310 Datasheet HTML 14Page - Dallas Semiconductor DS80C310 Datasheet HTML 15Page - Dallas Semiconductor DS80C310 Datasheet HTML 16Page - Dallas Semiconductor DS80C310 Datasheet HTML 17Page - Dallas Semiconductor DS80C310 Datasheet HTML 18Page - Dallas Semiconductor DS80C310 Datasheet HTML 19Page - Dallas Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 15 / 23 page
background image
DS80C310
15 of 23
EXTERNAL CLOCK CHARACTERISTICS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Clock High Time
tCHCX
10
ns
Clock Low Time
tCLCX
10
ns
Clock Rise Time
tCLCL
5
ns
Clock Fall Time
tCHCL
5
ns
SERIAL PORT MODE 0 TIMING CHARACTERISTICS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Serial Port Clock Cycle Time
SM2=0, 12 clocks per cycle
SM2=1, 4 clocks per cycle
tXLXL
12tCLCL
4tCLCL
ns
ns
Output Data Setup to Clock
Rising
SM2=0, 12 clocks per cycle
SM2=1, 4 clocks per cycle
tQVXH
10tCLCL
3tCLCL
ns
ns
Output Data Hold from
Clock Rising
SM2=0, 12 clocks per cycle
SM2=1, 4 clocks per cycle
tXHQX
2tCLCL
tCLCL
ns
ns
Input Data Hold after Clock
Rising
SM2=0, 12 clocks per cycle
SM2=1, 4 clocks per cycle
tXHDX
tCLCL
tCLCL
ns
ns
Clock Rising Edge to Input
Data Valid
SM2=0, 12 clocks per cycle
SM2=1, 4 clocks per cycle
tXHDV
11tCLCL
3tCLCL
ns
ns
EXPLANATION OF AC SYMBOLS
In an effort to remain compatible with the original 8051 family, this device specifies the same parameters
as such devices, using the same symbols. For completeness, the following is an explanation of the
symbols.
t
Time
A
Address
C
Clock
D
Input data
H
Logic level high
L
Logic level low
I
Instruction
P
PSEN
Q
Output data
R
RD
signal
V
Valid
W
WR
signal
X
No longer a valid logic level
Z
Tristate



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com