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DS80C310 数据表(PDF) 15 Page - Dallas Semiconductor |
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DS80C310 数据表(HTML) 15 Page - Dallas Semiconductor |
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15 / 23 page ![]() DS80C310 15 of 23 EXTERNAL CLOCK CHARACTERISTICS PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Clock High Time tCHCX 10 ns Clock Low Time tCLCX 10 ns Clock Rise Time tCLCL 5 ns Clock Fall Time tCHCL 5 ns SERIAL PORT MODE 0 TIMING CHARACTERISTICS PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Serial Port Clock Cycle Time SM2=0, 12 clocks per cycle SM2=1, 4 clocks per cycle tXLXL 12tCLCL 4tCLCL ns ns Output Data Setup to Clock Rising SM2=0, 12 clocks per cycle SM2=1, 4 clocks per cycle tQVXH 10tCLCL 3tCLCL ns ns Output Data Hold from Clock Rising SM2=0, 12 clocks per cycle SM2=1, 4 clocks per cycle tXHQX 2tCLCL tCLCL ns ns Input Data Hold after Clock Rising SM2=0, 12 clocks per cycle SM2=1, 4 clocks per cycle tXHDX tCLCL tCLCL ns ns Clock Rising Edge to Input Data Valid SM2=0, 12 clocks per cycle SM2=1, 4 clocks per cycle tXHDV 11tCLCL 3tCLCL ns ns EXPLANATION OF AC SYMBOLS In an effort to remain compatible with the original 8051 family, this device specifies the same parameters as such devices, using the same symbols. For completeness, the following is an explanation of the symbols. t Time A Address C Clock D Input data H Logic level high L Logic level low I Instruction P PSEN Q Output data R RD signal V Valid W WR signal X No longer a valid logic level Z Tristate |
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