DS80C310

3 of 23

PIN DESCRIPTION Table 1

DIP

PLCC

TQFP

SIGNAL

NAME

DESCRIPTION

40

44

38

20

22,23

1

16,17,

39

GND

GND- Digital circuit ground.

9

10

4

RST

RST - Input. The RST input pin contains a Schmitt voltage

input to recognize external active high reset inputs. The pin

also employs an internal pulldown resistor to allow for a

combination of wired OR external Reset sources.

18

19

20

21

14

15

XTAL2

XTAL1

XTAL1, XTAL2 - The crystal oscillator pins XTAL1 and

XTAL2 provide support for parallel resonant, AT cut

crystals. XTAL1 acts also as an input in the eve nt that an

external clock source is used in place of a crystal. XTAL2

serves as the output of the crystal amplifier.

29

32

26

PSEN

PSEN - Output. The Program Store Enable output. This

signal is commonly connected to external ROM memory as a

chip enable.

PSEN is active low. PSEN is driven high

when data memory (RAM) is being accessed through the bus

and during a reset condition.

30

33

27

ALE

ALE - Output. The Address Latch Enable output functions

as clock to latch the external address LSB from the

multiplexed address/data bus on Port 0. This signal is

commonly connected to the latch enable of an external 373

family transparent latch.ALE is forced high when the

DS80C310 is in a Reset condition.

39

38

37

36

35

34

33

32

43

42

41

40

39

38

37

36

37

36

35

34

33

32

31

30

AD0 (P0.0)

AD1 (P0.1)

AD2 (P0.2)

AD3 (P0.3)

AD4 (P0.4)

AD5 (P0.5)

AD6 (P0.6)

AD7 (P0.7)

AD0-7 (Port 0) - I/O. Port 0 is the multiplexed address/data

bus. During the time when ALE is high, the LSB of a

memory address is presented. When ALE falls to a logic 0,

the port transitions to a bidirectional data bus. This bus is

used to read external ROM and read/write external RAM

memory or peripherals. Port 0 has no true port latch and can

not be written directly by software. The reset condition of

Port 0 is high.

1-8

2-9

40-44

1-3

P1.0-P1.7

Port 1 - I/O. Port 1 functions as both an 8-bit bidirectional

I/O port and an alternate functional interface for Timer 2 I/O

and new External Interrupts. The reset condition of Port 1 is

with all bits at a logic 1. In this state, a weak pullup holds the

port high. This condition also serves as an input mode, since

any external circuit that writes to the port will overcome the

weak pullup. When software writes a 0 to any port pin, the

DS80C310 will activate a strong pulldown that remains on

until either a 1 is written or a reset occurs. Writing a 1 after

the port has been at 0 will cause a strong transition driver to

turn on, followed by a weaker sustaining pullup. Once the

momentary strong driver turns off, the port once again

becomes the output high (and input) state. The alternate

modes of Port 1 are outlined as follows: